AK8181A Datasheet, PDF (2/8 Pages) Asahi Kasei Microsystems – 3.3V LVPECL 1:4 Clock Fanout Buffer

AK8181A
Pin Descriptions
Package: 20-Pin TSSOP (Top View)
Pin No.
1
2
3
4
5
6
7
8,
9
10
11, 12
13
14, 15
16, 17
18
19, 20
Pin Name
VSS
CLK_EN
CLK_SEL
CLK0
NC
CLK1
NC
TEST
NC
VDD
Q3n, Q3
VDD
Q2n, Q2
Q1n, Q1
VDD
Q0n, Q0
Pin
Type
PWR
IN
IN
IN
--
IN
--
--
--
PWR
OUT
PWR
OUT
OUT
PWR
OUT
Pullup
down
--
PU
PD
PD
--
PD
--
--
--
--
--
--
--
--
--
--
Description
Negative supply
Synchronizing clock output enable (LVCMOS/LVTTL)
H: clock outputs follow clock input.
L: Q outputs are forced low, Qn outputs are forced high.
CLK Select Input (LVCMOS/LVTTL)
H: selects CLK1 input L: selects CLK0 input
LVCMOS/LVTTL Clock Input
No connect
LVCMOS/LVTTL Clock Input
No connect
Factory use. Internally pulled down. Leave open or tied to VSS.
No connect
Power supply
Differential clock output pair (LVPECL)
Power supply
Differential clock output (LVPECL)
Differential clock output (LVPECL)
Power supply
Differential clock output (LVPECL)
Ordering Information
Part Number
Marking
AK8181A
AK8181A
Shipping
Packaging
Tape and Reel
Package
20-pin TSSOP
Temperature
Range
-40 to 85 ℃
Nov-2011
MS1342-E-00
-2-