AK8181A Datasheet, PDF (4/8 Pages) Asahi Kasei Microsystems – 3.3V LVPECL 1:4 Clock Fanout Buffer

AK8181A
DC Characteristics
All specifications at VDD= 3.3V±5%, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
Input
CLK0, CLK1
High Voltage _{CLK_EN, CLK_SEL}
V_IH
Input
CLK0, CLK1
Low Voltage _{CLK_EN, CLK_SEL}
V_IL
Input
CLK0, CLK1, CLK_SEL
High Current _{CLK_EN}
I_H
Input
CLK0, CLK1, CLK_SEL
Low Current _{CLK_EN}
I_L
Output High Voltage⁽¹⁾
V_OH
Output Low Voltage⁽¹⁾
V_OL
Peak-to-Peak Output
Voltage Swing⁽¹⁾
V_SWING
Supply Current
I_DD
(1) .Outputs terminated with 50Ω to VDD-2V.
Vin=VDD
Vin=VDD
Vin=VSS
Vin=VSS
MIN
TYP
MAX Unit
2.0
2.0
-0.3
-0.3
-5
-150
VDD+0.3 V
VDD+0.3
1.3
V
0.8
150 μA
5
μA
μA
μA
VDD-1.4
VDD-0.9 V
VDD-2.0
VDD-1.7 V
0.6
1.0
V
35
50
mA
AC Characteristics
All specifications at VDD= 3.3V±5%, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP MAX Unit
Output Frequency
f_OUT
Propagation Delay⁽¹⁾
t_PD
266 MHz
0.6
1.4
ns
Output Skew⁽²⁾⁽³⁾
t_sk(O)
30
ps
Part-to-Part Skew⁽³⁾⁽⁴⁾
t_skPP
200 ps
Buffer Additive Jitter, RMS t_jit
12kHz to 20MHz
0.06
ps
Output Rise/Fall Time
t_r, t_f
20% to 80%
200
600 ps
Output Duty Cycle
DC_OUT
48
50
52
%
(1) Measured from the VDD/2 of the input to the differential output crossing point.
(2) Defined as skew between outputs at the same supply voltage and with equal load conditions.
(3) This parameter is defined in accordance with JEDEC Standard 65.
(4) Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
Nov-2011
MS1342-E-00
-4-