AK4551 Datasheet, PDF (6/15 Pages) Asahi Kasei Microsystems – LOW POWER & SMALL PACKAGE 20BIT CODEC

ASAHI KASEI
[AK4551]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=2.2 ∼ 3.6V; C_L=20pF)
Parameter
Master Clock Timing 256fs:
Pulse Width Low
Pulse Width High
384fs:
Pulse Width Low
Pulse Width High
512fs:
Pulse Width Low
Pulse Width High
Symbol
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
min
typ
max
2.048
11.2896
12.8
28
28
3.072
16.9344
19.2
23
23
4.096
22.5792
25.6
16
16
Units
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
LRCK Frequency
Duty Cycle
fs
8
44.1
45
Serial Interface Timing
SCLK Period
SCLK Pulse Width Low
Pulse Width High
LRCK Edge to SCLK “↑”
SCLK “↑” to LRCK Edge
LRCK Edge to SDTO (MSB)
SCLK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
(Note 8)
(Note 8)
tSCK
tSCKL
tSCKH
tLRS
tSLR
tDLR
tDSS
tSDH
tSDS
312.5
130
130
50
50
50
50
Reset Timing
50
kHz
55
%
ns
ns
ns
ns
ns
80
ns
80
ns
ns
ns
PWAD or PWDA Pulse Width
tPW
150
ns
PWAD “↑” to SDTO Valid (Note 9)
tPWV
2081
1/fs
Note 8. SCLK rising edge must not occur at the same time as LRCK edge.
Note 9. These cycles are the number of LRCK rising from PWAD rising.
MS0029-E-00
-6-
2000/5