AK4551 Datasheet, PDF (11/15 Pages) Asahi Kasei Microsystems – LOW POWER & SMALL PACKAGE 20BIT CODEC

ASAHI KASEI
[AK4551]
SYSTEM DESIGN
Figure 3 shows the system connection diagram. An evaluation board [AKD4551] is available which demonstrates
application circuit, optimum layout, power supply arrangements and measurement results.
Rch In
470
+
2.2n
Lch In
+
Analog Supply
2.2 ∼ 3.6V
470
2.2n
10u ₊
+
4.7u
0.1u
1 VCOM
AOUTR 16
2 AINR
AOUTL 15
3
4
0.1u
5
AINL
VSS
VDD
AK4551 ^{PWDA 14}
PWAD 13
Top View _{SCLK 12}
6 DEM0
MCLK 11
7 DEM1
LRCK 10
8 SDTO
SDTI 9
Reset
Reset
Controller
Mode
Control
Analog Ground
System Ground
Figure 3. System Connection Diagram Example
Notes:
- LRCK=fs, 40fs ≤ SCLK ≤ 96fs, MCLK=256fs/384fs/512fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive load.
- Electrolytic capacitor value of VCOM depends on low frequency noise of supply voltage.
MS0029-E-00
- 11 -
2000/5