AK4551 Datasheet, PDF (10/15 Pages) Asahi Kasei Microsystems – LOW POWER & SMALL PACKAGE 20BIT CODEC

ASAHI KASEI
[AK4551]
n Power-down & Reset
The ADC and DAC of AK4551 are placed in the power-down mode by bringing each power down pin, PWAD ,
PWDA = “L” independently and each digital filter is also reset at the same time. These resets should always be done after
power-up. In case of the ADC, an anlog initialization cycle starts after exiting the power-down mode. Therefore, the output
data, SDTO becomes available after 2081 cycles of LRCK clock. This initialization cycle does not affect the DAC
operation. Figure 2 shows the power-up sequence when the ADC is powered up before the DAC power-up.
PWAD
ADC Internal
State
PWDA
DAC Internal
State
ADC In
(Analog)
ADC Out
(Digital)
DAC In
(Digital)
DAC Out
(Analog)
Clock In
MCLK,LRCK,SCLK
External
Mute
Normal Operation
Power-down
2081/fs
Init Cycle
Normal Operation
Normal Operation
Power-down
Normal Operation
GD
GD
Idle Noise
GD
“0”data
“0”data
Idle Noise
GD
The clocks may be stopped.
Mute ON
Figure 2. Power-up Sequence
MS0029-E-00
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