AKD4634-A Datasheet, PDF (5/46 Pages) Asahi Kasei Microsystems – 16bit mono CODEC with MIC/SPK/VIDEO amplifier.

[AKD4634-A]
(2) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI pin)
a) Set up jumper pins of MCKI clock
X’tal of 12MHz, 13.5MHz, 24MHz or 27MHz can be set in X1. X’tal of 12 MHz (Default) is set on the
AKD4634-A. In this case, the AK4634 corresponds to PLL reference clock of 12MHz. In this evaluation mode,
the output clock from MCKO-pin of the AK4634 is supplied to a divider (U3: 74VHC4040), BICK and FCK
clocks are generated by the divider. Then “MCKO bit” in the AK4634 is set to “1”. When an external clock
through a RCA connector (J8: EXT/BICK) is supplied, select EXT on JP21 (MCLK_SEL) and short JP17
(XTE). JP23 (EXT1) and R26 should be properly selected in order to much the output impedance of the clock
generator.
JP17
XTE
JP21
MCLK_SEL
JP18
MKFS
XTL DIR EXT 256fs 512fs1024fs MCKO
b) Set up jumper pins of BICK clock
Input frequency of BICK should be set 64fs/32fs/16fs by JP19.
JP19
BICK_SEL
JP20
BICK
JP27
BICK
JP29
BICK_INV
64fsɹ 32fs^ɹɹ16fs^ɹɹ EXT INV THR ^{DIR ADC} INV THR
c) Set up jumper pins of FCK clock
JP22
FCK_SEL
JP28
FCK
2fs 1fs EXT
DIR ADC
d) Set up jumper pins of DATA
When the AK4634 is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the following.
JP30
SDTI
JP26
4632_SDTI
DIR
ADC
DAC/LOOP ^ADC
<KM088301>
-5-
2007/07