AKD4634-A Datasheet, PDF (4/46 Pages) Asahi Kasei Microsystems – 16bit mono CODEC with MIC/SPK/VIDEO amplifier.

[AKD4634-A]
(1) Evaluation of loop-back mode (A/D → D/A) : PLL, Master Mode (Default)
a) Set up jumper pins of MCKI clock
Set “No.8 of SW3” to “H”. X’tal of 12MHz, 13.5MHz, 24MHz or 27MHz can be set in X1. X’tal of 12MHz
(Default) is set on the AKD4634-A.
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz) through a RCA
connector (J8: EXT/BICK) is supplied, select EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1)
and R26 should be properly selected in order to much the output impedance of the clock generator.
JP17
XTE
JP21
MCLK_SEL
JP18
MKFS
XTL DIR EXT 256fs 512fs1024fs MCKO
b) Set up jumper pins of BICK clock
Output frequency (16fs/32fs/64fs) of BICK should be set by “BCKO1-0 bit” in the AK4634.
There is no necessity for set up JP19.
JP19
BICK_SEL
JP20
BICK
JP27
BICK
JP29
BICK_INV
64fsɹ 32fs^ɹɹ16fs^ɹɹ EXT INV THR ^{DIR ADC} INV THR
c) Set up jumper pins of FCK clock
JP22
FCK_SEL
JP28
FCK
DIR ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When the AK4634 is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the following.
JP30
SDTI
JP26
4632_SDTI
DIR
ADC
DAC/LOOP ^ADC
<KM088301>
-4-
2007/07