AKD4634-A Datasheet, PDF (10/46 Pages) Asahi Kasei Microsystems – 16bit mono CODEC with MIC/SPK/VIDEO amplifier.

[AKD4634-A]
„ Other jumper pins set up
1. JP1 (GND)
OPEN
SHORT
: Analog ground and Digital ground
: Separated.
: Common. (The connector “DGND” can be open.) <Default>
2. JP3 (AVDD_SEL) : AVDD of the AK4634
REG
: AVDD is supplied from the regulator (“AVDD” jack should be open). < Default >
AVDD
: AVDD is supplied from “AVDD ” jack.
3. JP4 (SVDD_SEL) : SVDD of the AK4634
REG
: SVDD is supplied from the regulator (“SVDD” jack should be open). < Default >
SVDD
: SVDD is supplied from “SVDD ” jack.
4. JP9 (DVDD_SEL) : DVDD of the AK4634
AVDD
: DVDD is supplied from “AVDD”. < Default >
DVDD
: DVDD is supplied from “DVDD ” jack.
5. JP10 (LVC_SEL) : Logic block of LVC is selected supply line.
DVDD
: Logic block of LVC is supplied from “DVDD”. < Default >
VCC
: Logic block of LVC is supplied from “VCC ” jack.
6. JP11 (VCC_SEL) : Logic block is selected supply line.
LVC
: Logic is supplied from supply line of LVC. < Default >
VCC
: Logic block of LVC is supplied from “VCC ” jack.
7. JP25 (MCKO_SEL) : Master Clock Frequency is selected clock from MCKO1 or MCKO2 of the AK4114.
MCKO1 : The check from MCKO1 of AK4114 is provided to MCKI of the AK4634. < Default >
MCKO2 : The check from MCKO2 of AK4114 is provided to MCKI of the AK4634.
8. JP102 (I2C)
OPEN
SHORT
: Control Interface is selected mode.
: 3-wire Serial Control Mode. < Default >
: I²C-bus Control Mode. (Not used in this board.)
9. JP103 (MCKO)
OPEN
SHORT
: Master Clock Frequency is selected from AK4634.
: Not supply.
: Supplied from AK4634. < Default >
<KM088301>
- 10 -
2007/07