AK5394A Datasheet, PDF (5/24 Pages) Asahi Kasei Microsystems – Super High Performance 192kHz 24-Bit ADC

ASAHI KASEI
[AK5394A]
Serial Data Clock Pin
SDATA is clocked out on the falling edge of SCLK.
Slave mode:
SCLK requires more than 48fs clock.
Master mode:
14 SCLK
I/O
AK5394A outputs following clocks as SCLK.
Normal Speed Mode: 128fs
Double Speed Mode: 64fs
Quad Speed Mode: 64fs
When RSTN pin = “L”, SCLK outputs “L”(normal/double speed mode) or
outputs the inverted MCLK (quad speed mode).
15 SDATA
Serial Data Output Pin
O
MSB first, 2’s complement.
Frame Synchronization Signal Pin
Slave mode:
When “H”, the data bits are clocked out on SDATA. In I²S mode, FSYNC is
16 FSYNC
I/O
don’t care.
Master mode:
FSYNC outputs 2fs clock.
FSYNC stays “L” during reset.
Master Clock Input Pin
DFS1 DFS0
MCLK
fs(typ)
17 MCLK
L
L
256fs
I
L
H
128fs
48kHz
96kHz
H
L
64fs
192kHz
H
H
(N/A)
(N/A)
Sampling Speed Select Pin 0
DFS1 DFS0
fs(typ)
18 DFS0
L
L
I
L
H
48kHz
96kHz
H
L
192kHz
H
H
(N/A)
High Pass Filter Enable Pin
19 HPFE
I “L”: Disable
“H”: Enable
20 DFS1
Sampling Speed Select Pin 1
I
(see #18 DFS0)
21 BGND
- Substrate Ground Pin, 0V
22 AGND
- Analog Ground Pin, 0V
23 VA
- Analog Supply Pin, 5V
24 AINR−
I Rch Analog negative input Pin
25 AINR+
I Rch Analog positive input Pin
26 VCOMR
O Rch Common Voltage Pin, 2.75V
Rch Negative Reference Voltage, 1.25V
27 VREFR−
O Normally connected to AGND with a large electrolytic capacitor and connected to
VREFR+ with a 0.22µF ceramic capacitor.
Rch Positive Reference Voltage, 3.75V
28 VREFR+
O Normally connected to AGND with a large electrolytic capacitor and connected to
VREFR- with a 0.22µF ceramic capacitor.
Note: All digital inputs should not be left floating.
MS0137-E-01
-5-
2002/07