AK5394A Datasheet, PDF (13/24 Pages) Asahi Kasei Microsystems – Super High Performance 192kHz 24-Bit ADC

ASAHI KASEI
[AK5394A]
„ System Clock Input
OPERATION OVERVIEW
The external clocks that are required to operate the AK5394A are MCLK, LRCK(fs) and SCLK. MCLK should be
synchronized with LRCK but the phase is free of care. Table 1 and 2 show the relationship between the sampling rate and
the frequencies of MCLK and SCLK.
As the AK5394A includes the phase detect circuit for LRCK, the AK5394A is reset automatically when the
synchronization is out of phase by changing the clock frequencies. Therefore, the reset is only needed for power-up.
All external clocks must be present unless RSTN pin = “L”, otherwise excessive current may result from abnormal
operation of internal dynamic logic.
Sampling Speed
Normal
Double
DFS0
L
H
DFS1
L
L
LRCK (fs)
∼ 54kHz
∼ 108kHz
SCLK (Slave Mode)
∼ 128fs
∼ 64fs
SCLK (Master Mode)
128fs
64fs
MCLK
256fs
128fs
Table 1. System Clocks
Quad
L
H
∼ 216kHz
∼ 64fs
64fs
64fs
LRCK (fs)
MCLK
SCLK
32kHz
8.1920MHz
∼ 4.0960MHz
44.1kHz
11.2896MHz
∼ 5.6448MHz
48kHz
12.2880MHz
∼ 6.1440MHz
96kHz
12.2880MHz
∼ 6.1440MHz
192kHz
12.2880MHz
∼ 12.288MHz
Table 2. Examples of System Clock Frequency
„ Serial Data Interface
The AK5394A supports four serial data formats that can be selected via SMODE1 and SMODE2 pins (Table 3). The data
format is MSB-first, 2’s complement.
Figure
Figure 1
Figure 2
Figure 3
Figure 4
SMODE2
L
L
H
H
SMODE1
Mode
L
Slave Mode
H
Master Mode
L
I²S Slave Mode
H
I²S Master Mode
Table 3. Serial I/F Formats
LRCK
Lch = H, Rch = L
Lch = H, Rch = L
Lch = L, Rch = H
Lch = L, Rch = H
MS0137-E-01
- 13 -
2002/07