AK5394A Datasheet, PDF (10/24 Pages) Asahi Kasei Microsystems – Super High Performance 192kHz 24-Bit ADC

ASAHI KASEI
[AK5394A]
SWITCHING CHARACTERISTICS
(Ta=25°C; VA=5.0V±5%; VD=3.0 ∼ 5.25V; C_L=20pF)
Parameter
Symbol
min
typ
Control Clock Frequency
Master Clock
fCLK
0.256
12.288
Pulse width Low tCLKL
29
Pulse width High tCLKH
29
Serial Data Output Clock (SCLK)
fSLK
6.144
Channel Select Clock (LRCK)
fs
1
48
duty cycle
25
Serial Interface Timing
(Note 12)
Slave Mode (SMODE1 = “L”)
SCLK Period
(Note 13)
Normal Speed Mode
tSLK
1/128fs
Double Speed Mode
tSLK
1/64fs
Quad Speed Mode
tSLK
1/64fs
SCLK Pulse width Low
tSLKL
33
Pulse width High
tSLKH
33
SCLK rising to LRCK Edge (Note 14)
tSLR
20
LRCK Edge to SCLK rising (Note 14)
tLRS
20
LRCK Edge to SDATA MSB Valid
tDLR
SCLK falling to SDATA Valid
SCLK falling to FSYNC Edge
tDSS
tSF
−20
Master Mode (SMODE1 = “H”)
SCLK Frequency
Normal Speed Mode
fSLK
128fs
Double Speed Mode
fSLK
64fs
Quad Speed Mode
fSLK
64fs
SCLK duty cycle
dSLK
50
FSYNC Frequency
fFSYNC
2fs
FSYNC duty cycle
SCLK falling to LRCK Edge
dFSYNC
50
tMSLR
−20
LRCK Edge to FSYNC rising
tLRF
1
SCLK falling to SDATA Valid
SCLK falling to FSYNC Edge
Reset / Calibration timing
tDSS
tSF
−20
RSTN Pulse width
tRTW
150
RSTN falling to CAL rising
tRCR
RSTN rising to CAL falling (Note 15)
Normal Speed Mode
tRCF
8704
Double Speed Mode
tRCF
17408
Quad Speed Mode
tRCF
34816
RSTN rising to SDATA Valid (Note 15)
Normal Speed Mode
tRTV
8719
Double Speed Mode
tRTV
17423
Quad Speed Mode
tRTV
34831
max
13.824
13.824
216
75
20
20
20
20
20
20
50
Notes: 12. Refer to Serial Data Interface Section.
13. At Slave Mode, SCLK must be continuously provided more than 16fs at LRCK=“H” and “L”.
14. Specified LRCK edges not to coincide with the rising edges of SCLK.
15. The number of the LRCK rising edges after RSTN pin brought high.
Units
MHz
ns
ns
MHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
Hz
Hz
%
Hz
%
ns
tSLK
ns
ns
ns
ns
1/fs
1/fs
1/fs
1/fs
1/fs
1/fs
MS0137-E-01
- 10 -
2002/07