AK4183_06 Datasheet, PDF (5/17 Pages) –

ASAHI KASEI
[AK4183]
DC Characteristics (Logic I/O)
Ta = -40 to 85°C, VCC = 2.5V to 3.6V
Parameter
Symbol
min.
typ.
max.
Units
“H” level input voltage
VIH
0.7xVCC
-
V
“L” level input voltage
VIL
-
0.3xVCC
V
Input Leakage Current
IILK
-10
10
µA
“H” level output voltage (PENIRQN pin@ Iout = -250µA)
VOH
VCC-0.4
V
“L” level output voltage (PENIRQN pin @ Iout = 250µA)
(SDA pin @ Iout = 3mA)
VOL
0.4
V
Tri-state Leakage Current
All pins except for XP, YP, XN, YN pins IOLK
-10
XP, YP, XN, YN pins
-50
10
µA
50
µA
Switching Characteristics
Ta = -40 to 85°C, VCC = 2.5V to 3.6V
Parameter (I²C Timing)
Symbol
min
typ
SCL clock frequency
fSCL
30
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first Clock pulse) tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
1.3
SDA Hold Time from SCL Falling
(Note 2)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise Suppressed
tSP
0
By Input Filter
Capacitive load on bus
Cb
Note 2: Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
max
Units
400
kHz
µs
µs
µs
µs
µs
µs
µs
0.3
µs
0.3
µs
µs
50
ns
400
pF
SDA
SCL
tBUF
tLOW tR
tHIGH tF
tHD:STA
Stop Start
tHD:DAT
tSU:DAT tSU:STA
Start
Figure 1 AK4183 Timing Diagram
VIH
VIL
tSP
VIH
VIL
tSU:STO
Stop
MS0500-E-00
5
2006/04