AK4183_06 Datasheet, PDF (14/17 Pages) –

ASAHI KASEI
[AK4183]
„ Pen Interrupt
The AK4183 has a pen-interrupt function to detect the pen touch on the touch panel. This function will use as the interrupt of the
microprocessor. Pen interrupt function is enabled at power-down state. YN driver is on and this pin is connected to GND at the
power down state. And XP pin is pulled up via an internal resister (Ri), typically 10KΩ. If the touch plate is touched by pen or
stylus, the current flows via <VCC>-<Ri>-<XP>-<the plates>-<YN>-<GND>. The resistance of the plate is generally 1KΩ or less,
PENIQRN pin is force to “L” level. If the pen is released, PENIRQN returns “H” level because two plates are disconnected, and the
current does not flow via two plates.
The transition of PENIRQN is related to PD0 bit. PD0 bit is updated as shown below. (Please see “power-down control” for the
detail. Once the control command with PD0= “1” is sent the pen-interrupt function is disabled.
The clock number under the write and the read operation refer to Figure 13 and Figure 14.
I.
The period from start condition to SCL7↓
The level transition of PENIRQN pin is determined by PD0 bit of the previous command. When the previous command
with PD0= “0” the pen-interrupt function will be enabled. PENIRQN pin is low when the panel is touch, PENIRQN pin is
“H” when the panel is untouched. When the previous command with PD0= “1” is sent PENIRQN pin is low regardless of
pen-touch
II. The period SCL7↓ to SCL8↑ on the write operation
The level of PENIRQN pin is always low regardless of PD0 bit and the state of panel (touched/untouched)
III. The period from SCL8↑ to SCL18↓ on the write operation
The level transition of PENIRQN pin is determined by PD0 bit of the previous command. When the previous command
with PD0= “0” the pen-interrupt function will be enabled. PENIRQN pin is low when the panel is touch, PENIRQN pin is
“H” when the panel is untouched. When the previous command with PD0= “1” is sent PENIRQN pin is low regardless of
pen-touch
IV. The period from SCL18↓ on the write operation to SCL7↓ on the read operation
The level of PENIRQN pin is determined by the A2 bit and PD0 bit of the present command. PENIRQN pin is always low
regardless pen-touch when command with A2 = “1” or PD0 = “1” is set. PENIRQN is determined by the pen-touch
(touched/untouched) when command with A2= “1” and PD0= “1” is sent.
V. The period from SCL7↓ to SCL21↓ on the write operation
The AD input will sample the hold and the conversion will be done during this period. PENIRQN is always low.
VI. The period after SCL21↓ on the read operation
The level transition of PENIRQN pin is determined by PD0 bit of the present command. When the present command with
PD0= “0” is sent the pen-interrupt function will be enabled. PENIRQN pin is low when the panel is touched. PENIRQN
pin is “H” when the panel is untouched. When the present command with PD0= “1” are sent PENIRQN pin is low
regardless of pen-touch.
It is recommended that the processor will mask the pseudo interrupt while the control command is issued or AD data is sent to
processor.
VCC
EN1
VCC
Ri =
10kΩ
VCC
EN2
Driver OFF
Driver ON
PENIRQN
To uP
PEN Interrupt
XP
YN
Figure 15 Pen interrupt function block
MS0500-E-00
14
2006/04