AK8448 Datasheet, PDF (44/53 Pages) Asahi Kasei Microsystems – 6-Channel Linear Sensor compatible 10 Bit 40 MSPS x 3 Analog Pre-Processor

ASAHI KASEI
[AK8448]
„ ADCK
A/D Conversion Rate mode and Total Pixel Rate mode
ADCK generates ADC conversion timing and ADC data output timing.
Whether to output data at both the rising edge and the falling edge of ADCK or to output
data at only the rising edge can be selected by ADCK Frequency mode register.
A/D conversion rate mode is a mode where data is output at both the rising edge and the
falling edge of ADCK.
In A/D conversion rate mode, input an ADCK clock of same frequency as ADC
conversion rate.
Total pixel rate mode is a mode where data is output at only the ADCK rising edge. In
this mode, input an ADCK clock of same frequency as a total sum of effective channels’
pixel rates.
For example, when to process a 20 MHz / channel sensor signal in 3 channel mode, a 20
MHz ADCK is input in A/D conversion rate mode which is equal to ADC conversion rate.
Maximum Conversion Rate
Maximum operating speed of ADC data output buffers DA0 ~ DA4, DB0 ~ DB4, DC0 ~
DC4 is designed to be 80 Mbps.
When a total pixel rate mode is selected as ADCK frequency mode, maximum sampling
rate per channel in 3 channel and 6 channel modes is limited by this output buffer speed.
For example, maximum conversion rate in 6 channel mode is 80 MSPS / 6 = 13.3 MSPS
per channel, and not 20 MSPS.
MS1513-E-00
44
2013/02