AK8448 Datasheet, PDF (2/53 Pages) Asahi Kasei Microsystems – 6-Channel Linear Sensor compatible 10 Bit 40 MSPS x 3 Analog Pre-Processor

ASAHI KASEI
[AK8448]
Functional Description of Each Block
… Clamp / CDS Sensor Interface Circuit
It samples the Image signal level from the sensor.
The AK8448 has 3 sampling modes – CDS mode, Clamp mode and DC direct-coupled mode.
There are 5 ,number of channel select modes – 1, 2, 3, 4 and 6 channels. Channel(s) to be used
is selected by the number of channel mode.
CDS circuits, DACs, PGAs and ADCs of the un-used channels are automatically powered-down.
… DAC
Offset addition D/A converter
This is a D/A converter to generate an offset voltage which is added to the sampled signal level at
the Sensor Interface part. Voltage range of DAC is ±298.7mV (typ.) and its resolution is 8 Bit. An
independent offset voltage can be set to each channel by register setting.
… PGA ( Programmable Gain Amplifier )
This is a programmable Gain amplifier to adjust signal amplitude of each channel. Adjustable
range is from 0 dB to 18.75 dB (typ.), and its resolution is 8 Bit.
An independent gain can be set to each channel by register setting.
… MUX
Channel Multiplexer
This is an Analog Switch to input in the time-division-multiplexed fashion the
simultaneously-sampled 2 channel signals to an ADC, in 4 channel mode and 6 channel mode.
In 4 channel mode and 6 channel mode, 10 Bit ADCs process dual channels in time-division-
multiplexed method.
… ADC
A/D Converter
This is a 10 Bit, 40 MSPS A/D converter to convert an Image signal level into digital data after
offset adjustment and gain adjustment are made. There are 3 ADCs and 2 channels are
connected to each ADC through a channel multiplexer.
… Output Control
ADC Output Data Control
Digital circuit to control the Output Form of ADC data. ADC data can be output in either 5 Bit-wide
or 10 Bit-wide by register setting.
In case of 5 Bit-wide data operation, the upper 5 Bit of the ADC data is output at the rising edge of
ACDK clock, and the lower 5 Bit data ,at the falling edge of ADCK.
In case of 10 Bit-wide data operation, ADC data from two different data channels are output at
the rising edge and at the falling edge of ADCK respectively.
It is also possible to output ADC data at only the falling edge of ADCK clock by register setting in
10 Bit-wide data operation.
MS1513-E-00
2
2013/02