AK8448 Datasheet, PDF (15/53 Pages) Asahi Kasei Microsystems – 6-Channel Linear Sensor compatible 10 Bit 40 MSPS x 3 Analog Pre-Processor

ASAHI KASEI
[AK8448]
„ Switching Characteristics 4 : in total pixel rate mode, CDS, Clamp modes
z Timing Diagrams ( 12 ) 10 Bit wide, 2 channel mode
z Timing Diagrams ( 14 ) 10 Bit wide, 3 channel mode
z Timing Diagrams ( 16 ) 10 Bit wide, 4 channel mode
z Timing Diagrams ( 18 ) 10 Bit wide, 6 channel mode
( AVDD = 3.0 ~ 3.6 V, DVDD = 3.0 ~ 3.6 V, Ta = 0 ~ 70°C)
No.
Parameter
Pin
Min. Typ. Max. Unit
Condition
1 ADCK Cycle Time ( T )
ADCK
12.5
333 ns 6ch mode
12.5
500
4ch mode
12.5
666
3ch mode
12.5
1000
2ch mode
2 ADCK Low Level Width
ADCK
4.6
ns
3 ADCK High Level Width
ADCK
4.6
ns
4 SHR, SHD Cycle Time
SHR, SHD
6T
ns 6ch mode
4T
4ch mode
3T
3ch mode
2T
2ch mode
5 SHR Pulse Width
SHR
8
ns
6 SHD Pulse Width
SHD
8
ns
7 SHD Set-up Time
SHD
0
( time to ADCK to rise )
T/2-2 ns
8 SHD Delay Time
SHD
10
ns
( note 1 )
11 SHR Aperture Delay
SHR
3.0
ns
12 SHD Aperture Delay
SHD
2.5
ns
11 Output Data Delay Time
( time from ADCK edge )
DA4~DA0 1
DB4~DB0
9
ns C=10pF
12 Pipe Line Delay
DA4~DA0
30
unit: 3ch,6ch mode
DB4~DB0
20
# of
ADC 2ch,4ch mode
K
cycle
s
13 SHD = “ H “ inhibit period SHD
( time till the first ADCK to
rise after SHD to fall )
3T+1
2T+1
ns 6ch mode
4ch mode
( note 1 )
Time from the ADCK edge where a falling edge of the internal A / D clock is generated.
In 2 channel, 4 channel modes, it is from ADCK to rise.
In 3 channel, 6 channel modes, it is from ADCK to fall.
Timings are specified at the points where specified levels by the DC Characteristics are
intersected.
MS1513-E-00
15
2013/02