AKD4569 Datasheet, PDF (4/27 Pages) Asahi Kasei Microsystems – Evaluation board Rev.A for AK4569

ASAHI KASEI
[AKD4569]
<Details for each evaluation mode>
(1) Loopback mode
MCLK, BICK and LRCK are fed from on-board DIR (AK4116). The clock source can be selected from on-board
X’tal oscillator or external master clock through a BNC connector (J8: EXTCLK).
CM1-0 bit (Addr=01H) of AK4116 should be set to “01” by the control software “akd4116-1.exe” packed with
AKD4569.
(2) Evaluation of ADC
AK4114 (DIT) generates audio bi-phase signal from received data and which is output through optical connector
(PORT4: TOTX141). It is possible to connect AKM’s D/A converter evaluation boards or the digital-amplifier
which equips DIR input. SW3 is used to set the interface format and clock mode of AK4114 (see DIP-SW set-up).
CM1-0 bit (Addr=01H) of AK4116 should be set to “01” by the control software “akd4116-1.exe” packed with
AKD4569.
(3) Evaluation of DAC (Default)
On-board DIR (AK4116) generates MCLK, BICK, LRCK and SDATA from the received data through optical
connector (TORX141). Used for the evaluation using CD test disk. Nothing should be connected to
PORT3(DSP).
(4) Feeding all signals externally
AK4569 can be evaluated by connecting DSP to PORT3(DSP).
n Other jumper pins setup
[JP2] (AINL): ADC Lch input select (Default: AINL1)
[JP3] (AINR): ADC Rch input select (Default: AINR1)
[JP5] (LIN/RIN/MIN): External analog input select (Default: MIN)
[JP10] (HPL): Headphone Lch output
Short: Output from J5(BNC) (Default)
Open: Output from J6(Headphone jack)
[JP11] (HPR): Headphone Rch output
Short: Output from J7(BNC) (Default)
Open: Output from J6(Headphone jack)
[JP12] (EXTCLK): Clock source
Short: External clock is input via J8(EXTCLK). On-chip X’tal (X1) should be removed.
Open: On-chip X’tal (X1) is used. (Default)
<KM074000>
-4-
2004/02