AKD4569 Datasheet, PDF (3/27 Pages) Asahi Kasei Microsystems – Evaluation board Rev.A for AK4569

ASAHI KASEI
n Evaluation mode
Applicable evaluation modes
(1) Loopback mode
(2) Evaluation of A/D part
(3) Evaluation of D/A part (Default)
(4) All interface signals including master clock are fed externally.
(1),(2),(4)
Analog Input
(2)
Digital Output
Printer Port
PC
(4)
DSP
Digital Input
(3)
PORT4
TOTX141
PORT1
µP I/F
J1
AINL
J2
AINR
AVDD
J3
L/R/MIN
J4
MOUT
J5
HPL
PORT3
DSP
PORT2
TORX141
J6
HP
DGND AGND
VD
DVDD HVDD
J7
HPR
REG
[AKD4569]
(3),(4)
Analog Input
(1),(3),(4)
Analog Output
0V
3V
Power Supply
Unit
Figure 3. Connection diagram for each evaluation mode
<Setup of jumper pins, signal I/O connector and DIR for each evaluation mode>
JP6 (MCLK)
JP7 (SDTI)
JP8 (BICK)
JP9 (LRCK)
Signal input
Signal output
AK4116(DIR)
Clock mode
(CM1-0 bit)
Mode (1)
short
ADC side
short
short
J1(AINL), J2(AINR)
J4(MOUT), J5(HPL),
J7(HPR), J6(HP)
Mode (2)
short
Don’t care
short
short
J1(AINL), J2(AINR)
PORT4(TOTX141)
Mode (3)
short
DIR side
short
short
PORT2(TORX141),
J3(LIN/RIN/MIN)
J4(MOUT), J5(HPL),
J7(HPR), J6(HP)
Mode (4)
open
open
open
open
PORT3(DSP)
J4(MOUT), J5(HPL),
J7(HPR), J6(HP)
X’tal mode
(CM1-0 = “01”)
X’tal mode
(CM1-0 = “01”)
PLL mode
(CM1-0 = “00”)
X’tal mode
(CM1-0 = “01”)
Table 2. Setup of jumper pins etc. for each evaluation mode
<KM074000>
-3-
2004/02