AK8815 Datasheet, PDF (4/37 Pages) Asahi Kasei Microsystems – NTSC/PAL Digital Video Encoder

ASAHI KASEI
[AK8815/16]
PIN FUNCTIONAL DESCRIPTION (preliminary)
No. Pin Name
A7
XTI/CLKIN
B6
XTO
B5
CLKMD
B9
CLKOUT
B7
CLKINV
J6
PDN
J5
RSTN
J4
SCLK
H4
SDI
H3
SDO
H5
CS
H8
D7
G8
D6
H9
D5
G9
D4
F8
D3
E8
D2
D8
D1
D9
D0
J7
HSYNC
H7
VSYNC
B3
VREF
I/O Function
Quartz crystal resonator connection pin ( to be grounded via a 18 pF capacitor as shown
in the recommended circuit ).
I NTSC: 24.5454 MHz / PAL: 29.50 MHz
Hi-Z input is acceptable to this pin at PDN = L.
Input from an external crystal oscillator should be connected to this pin.
Quartz crystal resonator connection pin ( to be grounded via a 22 pF capacitor as shown
O
in the recommended circuit ).
NTSC: 25.5454 MHz / PAL: 29.50 MHz
DVSS level is output on this pin at PDN = L.
Clock Mode setting pin. Should be connected to either DVDD or DGND.
I GND connection: when a crystal resonator is used
XVDD connection: when an external crystal oscillator is used
O
Clock output pin. NTSC: 24.5454 MHz / PAL: 29.50 MHz
This becomes Hi-Z output at PDN =L.
“L “ : data is latched with rising edge.
I
“H” : data is latched with falling edge.
Internal clock is inverted (internal operation timing edge is inverted. CLKOUT is not
affected). Connect to either DVDD or DGND.
Power Down Pin. After returning from PD mode to normal operation, RESET Sequence
I
should be done to AK8815/16.
“L “(GND level): Power-down
“H “: normal operation
Reset input pin. In order to initialize the device , an initialization must be made in
accordance with the reset sequence.
I “L “ : reset
“H “ : reset
Hi-Z input is acceptable to this pin at PDN = L.
I
Serial Data clock input pin. 15 MHz ( max )
Hi-Z input is acceptable to this pin at PDN = L.
I
Serial Data input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Serial Data output pin.
O This becomes high output at PDN = L.
This pin interfaces one-to-one with a controller through a dedicated pin.
Serial Data Chip Enable signal input pin.
This pin interfaces one-to-one with a controller through a dedicated pin.
I L : disabled condition ( un-selected )
H : enabled condition ( selected )
Hi-Z input is acceptable to this pin at PDN = L.
I
Data Video Signal input pin (MSB).
Hi-Z input is acceptable to this pin at PDN = L.
I
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
I
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
I
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
I
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
I
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
I
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
I
Data Video Signal input pin (LSB).
Hi-Z input is acceptable to this pin at PDN = L.
I
Horizontal SYNC signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
I
Vertical SYNC signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
O
On-chip VREF output pin. AVSS level is output on this pin at PDN = L.
Connect this pin to Analog Ground via a 0.1 uF or larger capacitor.
MS0331-E-00
4
2004 / 08