AK8815 Datasheet, PDF (33/37 Pages) Asahi Kasei Microsystems – NTSC/PAL Digital Video Encoder

ASAHI KASEI
[AK8815/16]
Device ID and Revision ID Register (R) [Address 0x03]
Sub Address 0x03
bit 7
bit 6
REV3
REV2
0
0
bit 5
REV1
0
bit 4
REV0
0
bit 3
DEV3
0
bit 2
DEV2
1
default Value 0x06
bit 1
bit 0
DEV1
DEV0
1
0
Device ID and Revision ID Register Definition
BIT Register Name
R/W
bit 0
DEV0
~
~
Device ID bit
R
bit 3
DEV2
bit 4
REV0
~
~
Revision ID bit
R
bit 7
REV3
Definition
Device ID bit to indicate Device ID.
Revision ID bit to indicate Revision ID. Revision ID is updated
When a possible software modification is made.
It is 0x00.
Reserved Register (R) [Address 0x04]
Sub Address 0x03
bit 7
bit 6
Reserved
Reserved
0
0
bit 5
Reserved
0
bit 4
Reserved
0
bit 3
Reserved
0
bit 2
Reserved
0
default Value 0x00
bit 1
bit 0
Reserved
Reserved
0
0
Device ID and Revision ID Register Definition
BIT Register Name
R/W
bit 0
~
Reserved Reserved bit
R/W
bit 7
Definition
Reserved
Input Control Register (R/W) [Address 0x05]
This is an out-of-standard quality input signal control register.
Sub Address 0x05
default Value 0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FLT
CBCR
VD2
VD1
VD0
HD2
HD1
HD0
0
0
0
0
0
0
0
0
Adjustment of Sync input timing is made
BIT Register Name
bit 0
HD0
~
~
HSYNC Input Delay
bit 2
HD2
bit 3
VD0
~
~
VSYNC Input Delay
bit 5
VD2
bit 6
CBCR
Exchange CbCr
bit 7
FLT
Y Flat Data
R/W Definition
R/W
HSYNC signal input is delayed by the set value.
HD [ 2:0 ] system clock count delay ( + 0 ~ + 7 CLK delay )
VD0 ~ VD2 VSYNC Input Delay
R/W VSYNC signal input is delayed by the set value.
VD [ 2:0 ] system clock count delay ( + 0 ~ + 7 CLK delay )
R/W Cb, Cr timing data are interchanged at CBCR = 1.
R/W ^{Y input data is linear- interpolated}
( averaging most adjacent data ).
MS0331-E-00
33
2004 / 08