AK1546 Datasheet, PDF (35/39 Pages) Asahi Kasei Microsystems – 3GHz Low Noise Integer-N Frequency Synthesizer

[AK1546]
14. Frequency Setting Timing Chart (Recommended Flow)
High
VDD1,VDD2
High
PDN
Registers
CP
Address2 Address0 Address1
{PD1}=1 Setting Setting
Hi-Z
Output1
Address2
{PD1}=0
Output2
Frequency Change Sequence (Controlled by {PD1} bit)
High
VDD1,VDD2
High
PDN
Registers
CP
Address3 Address0 Address1
{PD1}=0 Setting Setting
Hi-Z
Output1
Output2
Note)
Frequency Change Sequence (Controlled by Initialization Register)
Setting on Address3 is same as Address2. But {PD1} should be “0”.
Writing Address3 bring CP output to Hi-Z. After that, CP output restarts by the trigger of LE
pulse for Address1 writing to set the frequency.
MS1388-E-00
35
2012/3