AK1546 Datasheet, PDF (34/39 Pages) Asahi Kasei Microsystems – 3GHz Low Noise Integer-N Frequency Synthesizer

[AK1546]
13. Block Power-Up Timing Chart (Recommended Flow)
VDD1, VDD2
Write {PD1}=1, then raise PDN up
PDN
Internal LDO _0V
Registers
10ms
Registers value are defined
Address2 Address0 Address1
{PD1}=1 setting setting
Address2
{PD1}=0
1.9V
Write {PD1}=0
CP
Hi-Z
Output
Note)
Power-Up Sequence (Controlled by [PDN] pin)
After powers on AK1546, the initial registers value are not defined. It is required to write the
data in Addresses0~2 in order to commit it. It is recommended to bring PDN to high after
writing {PD1}=1 on Address2. It requires 10msec for LDO rising up after PDN rises up.
Writing {PD1}=0 should be done after LDO rises up.
VDD1,VDD2
PDN
Internal LDO _0V
10ms
Registers value are defined
Registers
Address2 Address0 Address1
{PD1}=1 setting setting
Address2
{PD1}=0
CP
Hi-Z
Undefined
1.9V
Write {PD1}=0
Output
Note)
Power-Up Sequence (VDD1/VDD2/PDN synchronous power-up)
After powers on AK1546, the initial registers value are not defined. It is required to write the
data in Addresses0~2 in order to commit it. It requires 10msec for LDO rising up after PDN
rises up. Writing {PD1}=0 should be done after LDO rises up.
MS1388-E-00
34
2012/3