AK4358_06 Datasheet, PDF (30/36 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit 8ch DAC with DSD Input

ASAHI KASEI
[AK4358]
Addr Register Name
0AH Control 3
Default
D7
D6
D5
D4
D3
D2
D1
D0
TDM1 TDM0 DCKS D/P DCKB DZFB ATS1 ATS0
0
0
0
0
0
0
0
0
ATS1-0: DATT Speed Setting (See Table 15)
Initial: “00”, mode 0
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection
1: DZF goes “L” at Zero Detection
DCKB: Polarity of DCLK (DSD Only)
0: DSD data is output from DCLK falling edge
1: DSD data is output from DCLK rising edge
D/P: DSD/PCM Mode Select
0: PCM Mode. SCLK, SDTI1-4, LRCK
1: DSD Mode. DCLK, DSDL1-4, DSDR1-4
When D/P changes form “1” to “0”, the AK4358 should be reset by PDN pin, PW bit or RSTN bit.
When D/P changes form “0” to “1”, the AK4358 should be reset by PW bit or RSTN bit.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs
1: 768fs
TDM0-1: TDM Mode Select (PCM only)
Mode
Normal
TDM256
TDM128
TDM1
0
0
1
TDM0
0
1
1
BICK
32fs∼
256fs fixed
128fs fixed
SDTI
1-4
1
1-2
Sampling Speed
Normal, Double, Quad Speed
Normal Speed
Normal, Double Speed
Addr Register Name
0DH DZF1 Control
Default
D7
D6
D5
D4
D3
D2
D1
D0
L1
R1
L2
R2
L3
R3
L4
R4
1
1
1
1
1
1
1
1
L1-4, R1-4: Zero Detect Flag Enable Bit for DZF1 pin
0: Disable
1: Enable
Addr
0EH
0FH
Register Name
DZF2 Control
DZF3 Control
Default
D7
D6
D5
D4
D3
D2
D1
D0
L1
R1
L2
R2
L3
R3
L4
R4
L1
R1
L2
R2
L3
R3
L4
R4
0
0
0
0
0
0
0
0
L1-4, R1-4: Zero Detect Flag Enable Bit for DZF2,3 pins
0: Disable
1: Enable
MS0203-E-01
- 30 -
2006/02