AK4358_06 Datasheet, PDF (24/36 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit 8ch DAC with DSD Input

ASAHI KASEI
[AK4358]
„ Register Control Interface
The AK4358 controls its functions via registers. 2 types of control mode write internal registers. In the I²C-bus mode, the
chip address is determined by the state of the CAD0 and CAD1 inputs. In 3-wire mode, the CAD1 input is fixed to “1”
and Chip Address C0 is determined by the state of the CAD0 pin. PDN = “L” initializes the registers to their default
values. Writing “0” to the RSTN bit resets the internal timing circuit, but the register data is not initialized.
* The AK4358 does not support the read command.
* When the AK4358 is in the power down mode (PDN = “L”) or the MCLK is not provided, Writing to control
register is invalid.
Function
Manual Setting Mode
De-emphasis
DZFE
SMUTE
Audio data format
DSD mode
Attenuator
Slow roll-off response
Pin set-up
O
X
X
X
DIF0
X
X
X
Register set-up
O
O
O
O
O
O
O
O
Table 17. Function Table (O: Supported, X: Not supported)
(1) 3-wire Serial Control Mode (I2C = “L”)
3-wire µP interface pins, CSN, CCLK and CDTI, write internal registers. The data on this interface consists of Chip
Address (2bits, C1/0; C1 is fixed to “1” and C0=CAD0), Read/Write (1bit; fixed to “1”, Write only), Register Address
(MSB first, 5bits) and Control Data (MSB first, 8bits). The AK4358 latches the data on the rising edge of CCLK, so data
should clocked in on the falling edge. The writing of data becomes valid by the rising edge of CSN. The clock speed of
CCLK is 5MHz (max).
CSN
CCLK
CDTI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (C1= “1”, C0=CAD0)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 17. Control I/F Timing
MS0203-E-01
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2006/02