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AK4358_06 Datasheet, PDF (21/36 Pages) Asahi Kasei Microsystems – 192kHz 24-Bit 8ch DAC with DSD Input | |||
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ASAHI KASEI
[AK4358]
 Zero Detection
When the input data at all channels are continuously zeros for 8192 LRCK cycles, the AK4358 has Zero Detection like
Table 16. DZF pin immediately goes to âLâ if input data of each channel is not zero after going DZF âHâ. If RSTN bit is
â0â, DZF pin goes to âHâ. DZF pin goes to âLâ at 4~5LRCK if input data of each channel is not zero after RSTN bit
returns to â1â. Zero detect function can be disabled by DZFE bit. In this case, all DZF pins are always âLâ. When one of
PW1-4 bit is set to â0â, the input data of DAC that the PW bit is set to â0â should be zero in order to enable zero detection
of the other channels. When all PW1-4 bits are set to â0â, DZF pin fixes âLâ. DZFB bit can invert the polarity of DZF pin.
DZF Pin
DZF1
DZF2
DZF3
Operations
ANDed output of zero detection flag of each channel set to â1â in 0DH register
ANDed output of zero detection flag of each channel set to â1â in 0EH register
ANDed output of zero detection flag of each channel set to â1â in 0FH register
Table 16. DZF pins Operation
 Soft Mute Operation
Soft mute operation is performed at digital domain. When the SMUTE bit goes to â1â, the output signal is attenuated by
-â during ATT_DATAÃATT transition time (Table 15) from the current ATT level. When the SMUTE bit is returned to
â0â, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATAÃATT
transition time. If the soft mute is cancelled before attenuating to -â after starting the operation, the attenuation is
discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source
without stopping the signal transmission.
SMUTE bit
ATT Level
(1)
Attenuation
(1)
(3)
-â
GD
GD
(2)
AOUT
DZF pin
(4)
8192/fs
Notes:
(1) ATT_DATAÃATT transition time (Table 15). For example, in Normal Speed Mode, this time is 1792LRCK cycles
(1792/fs) at ATT_DATA=128.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -â after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to
âHâ. DZF pin immediately goes to âLâ if input data are not zero after going DZF âHâ.
Figure 14. Soft Mute and Zero Detection
MS0203-E-01
- 21 -
2006/02
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