AK4529 Datasheet, PDF (26/38 Pages) Asahi Kasei Microsystems – High Performance Multi-channel Audio CODEC

ASAHI KASEI
[AK4529]
(2) I²C-bus Control Mode (I2C= “H”)
AK4529 supports the standard-mode I²C-bus (max:100kHz). Then AK4529 cannot be incorporated in a fast-mode
I²C-bus system (max:400kHz). The CSN pin should be connected to DVDD at the I²C-bus mode.
Figure 13 shows the data transfer sequence at the I²C-bus mode. All commands are preceded by a START condition.
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (figure 17). After the
START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data
direction bit (R/W) (figure 14). The most significant five bits of the slave address are fixed as “00100”. The next two
bits are CAD1 and CAD0 (device address bits). These two bits identify the specific device on the bus. The hard-
wired input pins (CAD1 pin and CAD0 pin) set them. If the slave address match that of the AK4529 and R/W bit is
“0”, the AK4529 generates the acknowledge and the write operation is executed. If R/W bit is “1”, the AK4529
generates the not acknowledge since the AK4529 can be only a slave-receiver. The master must generate the
acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (figure 18).
The second byte consists of the address for control registers of the AK4529. The format is MSB first, and those most
significant 3-bits are fixed to zeros (figure 15). Those data after the second byte contain control data. The format is
MSB first, 8bits (figure 16). The AK4529 generates an acknowledge after each byte has been received. A data
transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA
line while SCL is HIGH defines a STOP condition (figure 17).
The AK4529 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the
AK4529 generates an acknowledge, and awaits the next data again. The master can transmit more than one byte
instead of terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal
5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address
exceed 1FH prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data
will be overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (figure 19) except for the START and the STOP
condition.
SDA
S
T
S
A
R/W
T
R
O
T
P
S
Slave
Address
Sub
Address(n)
Data(n)
Data(n+1)
Data(n+x) P
A
A
A
A
A
A
C
C
C
C
C
C
K
K
K
K
K
K
Figure 13. Data transfer sequence at the I²C-bus mode
0
0
1
0
0 CAD1 CAD0 R/W
(Those CAD1/0 should match with CAD1/0 pins)
Figure 14. The first byte
0
0
0
A4
A3
A2
A1
A0
Figure 15. The second byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 16. Byte structure after the second byte
MS0082-E-00
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