AK4529 Datasheet, PDF (25/38 Pages) Asahi Kasei Microsystems – High Performance Multi-channel Audio CODEC

ASAHI KASEI
[AK4529]
n Serial Control Interface
The AK4529 can control its functions via registers. Internal registers may be written by 2 types of control mode. The chip
address is determined by the state of the CAD0 and CAD1 inputs. PDN = “L” initializes the registers to their default
values. Writing “0” to the RSTN bit can initialize the internal timing circuit. But in this case, the register data is not be
initialized. When the state of P/S pin is changed, the AK4529 should be reset by PDN pin.
* Writing to control register is invalid when PDN = “L” or the MCLK is not fed.
* AK4529 does not support the read command.
(1) 3-wire Serial Control Mode (I2C = “L”)
Internal registers may be written to the 3 wire µP interface pins (CSN, CCLK and CDTI). The data on this interface
consists of Chip address (2bits, CAD0/1), Read/Write (1bit, Fixed to “1”, Write only), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. For write operations, data is latched after a low-to-high transition of CSN. The clock
speed of CCLK is 5MHz(max). The CSN pin should be held to “H” except for access.
CSN
CCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (C1=CAD1, C0=CAD0)
R/W: Read/Write (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 12. 3-wire Serial Control I/F Timing
MS0082-E-00
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