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AK4529 Datasheet, PDF (24/38 Pages) Asahi Kasei Microsystems – High Performance Multi-channel Audio CODEC | |||
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ASAHI KASEI
[AK4529]
n Reset Function
When RSTN = â0â, ADC and DACs are powered-down but the internal register are not initialized. The analog outputs go
to VCOM voltage, DZF1-2 pins go to âHâ and SDTO pin goes to âLâ. Because some click noise occurs, the analog output
should muted externally if the click noise influences system application. Figure 11 shows the power-up sequence.
RSTN bit
Internal
RSTN bit
ADC Internal
State
DAC Internal
State
ADC In
(Analog)
ADC Out
(Digital)
DAC In
(Digital)
DAC Out
(Analog)
Clock In
MCLK,LRCK,SCLK
DZF1/DZF2
Normal Operation
4~5/fs (9)
1~2/fs (9)
Digital Block Power-down
516/fs (1)
Init Cycle
Normal Operation
Normal Operation
Digital Block Power-down
GD (2)
Normal Operation
GD
(3)
â0âdata
(2)
GD
â0âdata
(6) (5)
(7)
Donât care
(6)
4â¼5/fs (8)
(4)
GD
Notes:
(1) The analog part of ADC is initialized after exiting the reset state.
(2) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(GD).
(3) ADC output is â0â data at the power-down state.
(4) Click noise occurs when the internal RSTN bit becomes â1â. Please mute the digital output externally if the click
noise influences system application.
(5) The analog outputs go to VCOM voltage.
(6) Click noise occurs at 4â¼5/fs after RSTN bit becomes â0â, and occurs at 1â¼2/fs after RSTN bit becomes â1â. This
noise is output even if â0â data is input.
(7) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode. When exiting the reset mode, â1â
should be written to RSTN bit after the external clocks (MCLK, BICK and LRCK) are fed.
(8) DZF pins go to âHâ when the RSTN bit becomes â0â, and go to âLâ at 6~7/fs after RSTN bit becomes â1â.
(9) There is a delay, 4~5/fs from RSTN bit â0â to the internal RSTN bit â0â.
Figure 11. Reset sequence example
MS0082-E-00
- 24 -
2001/3
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