AK4160 Datasheet, PDF (24/40 Pages) Asahi Kasei Microsystems – 16-channel Capacitive Touch Sensor IC

[AK4160]
Threshold Register (THn: n=0~15)
Address 0x25/0x27/…/0x43 (W/R) Default 0x00
Description
D7
D6
CSn Touch Threshold
T8Xn
TTn[6]
D5
TTn[5]
D4
TTn[4]
D3
TTn[3]
D2
TTn[2]
D1
TTn[1]
D0
TTn[0]
Address 0x26/0x28/…/0x44 (W/R) Default 0x00
Description
D7
D6
CSn Release Threshold
R8Xn
RTn[6]
D5
RTn[5]
D4
RTn[4]
D3
RTn[3]
D2
RTn[2]
D1
RTn[1]
D0
RTn[0]
Bits
D7
D6-D0
Name
T8Xn
TTn
Description
The touch threshold of the terminal CSn is increased by a factor of eight.
The touch threshold of the terminal CSn is set.
T8Xn=0: The threshold is 0~127 (Step 1)
T8Xn=1: The threshold is 0~1016 (Step 8)
Bits
Name
Description
D7
R8Xn
The release threshold of the terminal CSn is increased by a factor of eight.
D6-D0
RTn
The release threshold of the terminal CSn is set.
R8Xn=0: The threshold is 0~127 (Step 1)
R8Xn=1: The threshold is 0~1016 (Step 8)
The threshold register should not be updated in run-mode.
When the sense terminal is set to GPIO, the threshold register becomes a GPIO control register GPCn (n=0~7).
Address
0x25 – 0x26
0x27 – 0x28
0x29 – 0x2A
0x2B – 0x2C
0x2D – 0x2E
0x2F – 0x30
0x31 – 0x32
0x33 – 0x34
0x35 – 0x36
0x37 – 0x38
0x39 – 0x3A
0x3B – 0x3C
0x3D – 0x3E
0x3F – 0x40
0x41 – 0x42
0x43 – 0x44
CS
GPIO
CS0 Threshold Register
-
CS1 Threshold Register
-
CS2 Threshold Register
-
CS3 Threshold Register
-
CS4 Threshold Register
-
CS5 Threshold Register
-
CS6 Threshold Register
-
CS7 Threshold Register
-
CS8 Threshold Register
GPIO7 Control Register
CS9 Threshold Register
GPIO6 Control Register
CS10 Threshold Register
GPIO5 Control Register
CS11 Threshold Register
GPIO4 Control Register
CS12 Threshold Register
GPIO3 Control Register
CS13 Threshold Register
GPIO2 Control Register
CS14 Threshold Register
GPIO1 Control Register
CS15 Threshold Register
GPIO0 Control Register
Table 7. CS Threshold Register and GPIO Control Register
GPIO Control Register (GPCn: n=0~7)
CS8~CS15 can be used as GPIO by setting GPIO enable register (Addr 0x5E). In this case, the threshold register works as
the GPIO control register. The bit allocation of the GPIO control register at the input setting (DIR bit = “0”) is different
from the allocation at the output setting (DIR bit = “1”).
MS1313-E-01
- 24 -
2011/11