AK4160 Datasheet, PDF (20/40 Pages) Asahi Kasei Microsystems – 16-channel Capacitive Touch Sensor IC

[AK4160]
■ Register definition
Touch Status Register
Address 0x00 (R) Default 0x00
Description
D7
Touch Status
TS[15]
Address 0x01 (R) Default 0x00
Description
D7
Touch Status
TS[7]
D6
TS[14]
D5
TS[13]
D6
TS[6]
D5
TS[5]
D4
TS[12]
D3
TS[11]
D4
TS[4]
D3
TS[3]
D2
TS[10]
D2
TS[2]
D1
TS[9]
D1
TS[1]
D0
TS[8]
D0
TS[0]
Bits
Name
Description
15-0
TS
Touch Status for Each Sense Terminal
0: Release
1: Touch
IRQ Status Register
Address 0x02 (R) Default 0x00
Description
D7
D6
D5
IRQ Status
DRDY TOUCH
REL
D4
D3
D2
D1
D0
ACF
RANGE
GPIN Reserved Reserved
Bits
Name
Description
D7
DRDY
Data Ready Interrupt
The DRDY bit is set to “1” in the status of data ready.
When the data ready interrupt is invalid, this bit is fix to “0”.
D6
TOUCH Touch Interrupt
The TOUCH bit is set to “1” in the status of touch transition.
When touch interrupt is invalid, this bit is fix to “0”. The sense terminal connected
to the interrupt is selected by IRQM register. (Address 0x66~0x67, 0x6A~0x6B,
0x6E~0x6F)
D5
REL
Release Interrupt
The REL bit is set to “1” in the status of release transaction.
When release interrupt is invalid, this bit is fix to “0”. The sense terminal
connected to the interrupt is selected by IRQM register. (Address 0x66~0x67,
0x6A~0x6B, 0x6E~0x6F)
D4
ACF
Automatic Setting Fail Interrupt
The ACF bit is set to “1”, when the measured value of the sense terminal is over
the upper limit at the termination of automatic setting. When the automatic setting
or the automatic setting fail interrupt is invalid, this bit is fix to “0”.
D3
RANGE Range Over Interrupt
The RANGE bit is set to “1”, when the measured value of the sense terminal is
over the upper limit. When the automatic resetting or the range over interrupt is
invalid, the bit is fix to “0”.
D2
GPIN
GPIO Input Interrupt
The GPIN bit is set to “1” when a GPIO Input Interrupt occurs. When the GPIO
input interrupt is invalid, the bit is fix to “0”.
D1-D0 Reserved Reserved
When the IRQ bit (Addr 0x03 IRQ2-0 bits) with permission of interrupt is cleared, these bits are also cleared.
MS1313-E-01
- 20 -
2011/11