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AK4702EQ Datasheet, PDF (21/39 Pages) Asahi Kasei Microsystems – 2ch DAC with AV SCART switch | |||
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ASAHI KASEI
[AK4702EQ]
The Figure 7 shows an example of the system timing at the power-down and power-up by PDN pin.
PDN pin
MUTE bit
STBY bit
â1â (default)
â1â (default)
âStand-byâ
â0â
âMuteâ
â1â
â0â
âStand-byâ
â0â
â1â
â1â
Clock in
Data in
D/A Out
(internal)
donât care (2)
donât care
normal operation
â0â
Audio data
GD (1)
donât care (2)
â0â
donât care
GD (1)
TV-Source
select
fixed to VCR in(Loop-through)
VCR in
(default)
DAC
(4)
offset calibration
VCR in
TV out
VCR in
VCR in
(3)
Notes:
(1) The analog output corresponding to the digital input has a group delay, GD.
(2) The external clocks (MCLK, BICK and LRCK) can be stopped in standby mode.
(3) Please mute the analog outputs externally if click noise(3) adversely affects the system.
(4) In case of the CAL bit = â1â, the offset calibration is always executed when the source of TVOUT is switched to
DAC after the STBY bit is changed to â0â. To disable this function, set the CAL bit = â0â.
Figure 7. Power-down/up sequence example
MS0424-E-00
- 21 -
2005/09
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