AK4702EQ Datasheet, PDF (16/39 Pages) Asahi Kasei Microsystems – 2ch DAC with AV SCART switch

ASAHI KASEI
[AK4702EQ]
OPERATION OVERVIEW
„ System Clock
The external clocks required to operate the DAC section of AK4702 are MCLK, LRCK and BICK. The master clock
(MCLK) corresponds to 256fs or 384fs. MCLK frequency is automatically detected, and the internal master clock
becomes 256fs. The MCLK should be synchronized with LRCK but the phase is not critical. Table 1 illustrates
corresponding clock frequencies. All external clocks (MCLK, BICK and LRCK) should always be present whenever the
DAC section of AK4702 is in the normal operating mode (STBY bit = “0”). If these clocks are not provided, the AK4702
may draw excess current because the device utilizes dynamically refreshed logic internally. The DAC section of AK4702
should be reset by STBY = “0” after threse clocks are provided. If the external clocks are not present, place the AK4702
in power-down mode (STBY bit = “1”). After exiting reset at power-up etc., the AK4702 remains in power-down mode
until MCLK and LRCK are input.
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
MCLK
256fs
384fs
8.1920MHz 12.2880MHz
11.2896MHz 16.9344MHz
12.2880MHz 18.4320MHz
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
„ Audio Serial Interface Format
Table 1. System clock example
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0 and DIF1 bits can select four formats in serial
mode as shown in Table 2. In all modes, the serial data is MSB-first, 2’s compliment format and is latched on the rising
edge of BICK. Mode 2 can also be used for 16 MSB justified formats by zeroing the unused two LSBs.
Mode
0
1
2
3
DIF1
0
0
1
1
DIF0
0
1
0
1
SDTI Format
16bit LSB Justified
18bit LSB Justified
18bit MSB Justified
18bit I²S Compatible
BICK
≥32fs
≥36fs
≥36fs
≥36fs or
32fs
Figure
Figure 3
Figure 3
Figure 4
Figure 5
Default
Table 2. Audio Data Formats
LRCK
BICK
SDTI
Mode 0
Don’t care
15:MSB, 0:LSB
15 14
0 Don’t care
15 14
0
SDTI
Mode 1
Don’t care
17 16 15 14
0 Don’t care
17 16 15 14
0
17:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 0,1 Timing
MS0424-E-00
- 16 -
2005/09