AK4702EQ Datasheet, PDF (12/39 Pages) Asahi Kasei Microsystems – 2ch DAC with AV SCART switch

ASAHI KASEI
[AK4702EQ]
Note: 14. TVRC, TVG, TVB.
Note: 15. Refer the Figure 1.
Video Signal Output
C2
R1
75 ohm
C1
R2
75 ohm
max: 15pF
max: 400pF
Figure 1. Load Resistance R1+R2, and Load Capacitance C1 and C2.
Note: 16. AC load. Refer the Figure 2.
Video Signal Output
C2
max: 15pF
R1
20k ohm
(AC load)
Figure 2. Load Resistance R1 and Load Capacitance C1
SWITCHING CHARACTERISTICS
(Ta = 25°C; VP=10.0 ∼ 12.6V, VD = 4.75 ∼ 5.25V, VVD1=VVD2 = 4.75 ∼ 5.25V; C_L = 20pF)
Parameter
Symbol
Min
typ
max
Master Clock Frequency 256fs:
fCLK
2.048
12.8
Duty Cycle
dCLK
40
60
384fs:
fCLK
3.072
19.2
Duty Cycle
dCLK
40
60
LRCK Frequency
fs
8
50
Duty Cycle
Duty
45
55
Audio Interface Timing
BICK Period
tBCK
312.5
BICK Pulse Width Low
tBCKL
100
Pulse Width High
tBCKH
100
BICK “↑” to LRCK Edge (Note: 17)
tBLR
50
LRCK Edge to BICK “↑” (Note: 17)
tLRB
50
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
Control Interface Timing (I²C Bus):
SCL Clock Frequency
fSCL
-
100
Bus Free Time Between Transmissions
tBUF
4.7
-
Start Condition Hold Time
tHD:STA
4.0
-
(prior to first clock pulse)
Clock Low Time
tLOW
4.7
-
Clock High Time
tHIGH
4.0
-
Setup Time for Repeated Start Condition
tSU:STA
4.7
-
SDA Hold Time from SCL Falling (Note: 18) tHD:DAT
0
-
SDA Setup Time from SCL Rising
tSU:DAT
0.25
-
Rise Time of Both SDA and SCL Lines
tR
-
1.0
Fall Time of Both SDA and SCL Lines
tF
-
0.3
Setup Time for Stop Condition
tSU:STO
4.0
-
Pulse Width of Spike Noise
tSP
0
50
Suppressed by Input Filter
Reset Timing
PDN Pulse Width
(Note: 19)
tPD
150
Units
MHz
%
MHz
%
kHz
%
ns
ns
ns
ns
ns
ns
ns
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
MS0424-E-00
- 12 -
2005/09