AK4112B Datasheet, PDF (21/30 Pages) Asahi Kasei Microsystems – HIGH FEATURE 96kHz 24BIT DIR

ASAHI KASEI
[AK4112B]
„ Register Map
Addr Register Name
D7
00H Clock & Power down Control
0
01H Input/Output Control
MPAR
02H Format & De-emphasis Control V/TX
03H Receiver status 1
ERF
04H Receiver status 2
CV
05H Channel A Status Byte 0
CA7
06H Channel A Status Byte 1
CA15
07H Channel A Status Byte 2
CA23
08H Channel A Status Byte 3
CA31
09H Channel B Status Byte 0
CB7
0AH Channel B Status Byte 1
CB15
0BH Channel B Status Byte 2
CB23
0CH Channel B Status Byte 3
CB31
0DH Burst Preamble Pc Byte 0
PC7
0EH Burst Preamble Pc Byte 1
PC15
0FH Burst Preamble Pd Byte 0
PD7
10H Burst Preamble Pd Byte 1
PD15
11H Count Control
0
D6
D5
D4
D3
D2
D1
BCU CM1 CM0 OCKS1 OCKS0 PWN
MSTC CS12 TXE IPS1 IPS0 OPS1
DIF2 DIF1 DIF0 DEAU DEM1 DEM0
0 AUDION AUTO PEM FS1 FS0
STC CRC UNLOCK V FRERR BIP
CA6 CA5 CA4 CA3 CA2 CA1
CA14 CA13 CA12 CA11 CA10 CA9
CA22 CA21 CA20 CA19 CA18 CA17
CA30 CA29 CA28 CA27 CA26 CA25
CB6 CB5 CB4 CB3 CB2 CB1
CB14 CB13 CB12 CB11 CB10 CB9
CB22 CB21 CB20 CB19 CB18 CB17
CB30 CB29 CB28 CB27 CB26 CB25
PC6 PC5 PC4 PC3 PC2 PC1
PC14 PC13 PC12 PC11 PC10 PC9
PD6 PD5 PD4 PD3 PD2 PD1
PD14 PD13 PD12 PD11 PD10 PD9
0
0
0
0
EFH1 EFH0
D0
RSTN
OPS0
DFS
RFS96
PAR
CA0
CA8
CA16
CA24
CB0
CB8
CB16
CB24
PC0
PC8
PD0
PD8
XFS96
Notes:
For addresses from 12H to 1FH, data must not be written.
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the internal timing is reset and the registers are initialized to their default values.
All data can be written to the register even if PWN bit is “0”.
MS0078-E-02
- 21 -
2004/04