AK4112B Datasheet, PDF (13/30 Pages) Asahi Kasei Microsystems – HIGH FEATURE 96kHz 24BIT DIR

ASAHI KASEI
[AK4112B]
„ System Reset and Power-Down
The AK4112B has a power-down mode for all circuits by PDN pin can be partially powerd-down by PWN bit. The
RSTN bit initializes the register and resets the internal timing. In Parallel Mode, only the control by PDN pin is enabled.
The AK4112B should be reset once by bringing PDN pin = “L” upon power-up.
PDN Pin (Pin #7):
All analog and digital circuit are placed in the power-down and reset mode by bringing PDN= “L”. All the
registers are initialized, and clocks are stopped. Reading/Witting to the register are disabled.
RSTN Bit (Address 00H; D0):
All the registers except PWN and RSTN are initialized by bringing RSTN bit = “0”. The internal timings are
also initialized. Witting to the register is not available except PWN and RSTN. Reading to the register is
disabled.
PWN Bit (Address 00H; D1):
The clock recovery part is initialized by bringing PWN bit = “0”. In this case, clocks are stopped. The registers
are not initialized and the mode settings are kept. Writing and Reading to the registers are enabled.
„ Biphase Input and Through Output
Four receiver inputs (RX1-4) are available in Serial Control Mode. Each input includes amplifier corresponding to
unbalance mode and can accept the signal of 350mV or more. IPS0-1 selects the receiver channel, and OPS0-1 selects the
source of the bit stream driving the transmit channel (TX). The TX output can be stopped by setting TXE bit “0”.
IPS1 IPS0 INPUT Data
0
0
0
1
1
0
1
1
RX1
Default
RX2
RX3
RX4
Table 9. Recovery data select
OPS1
0
0
1
1
OPS0
0
1
0
1
INPUT Data
RX1
RX2
RX3
RX4
Default
Table 10. Output data select
MS0078-E-02
- 13 -
2004/04