AK8443 Datasheet, PDF (2/29 Pages) Asahi Kasei Microsystems – 16bit 30MSPS video ADC with CCD/CIS interface

[AK8443]
Circuit Block
„ Clamp, CDS Block
The clamp circuit and correlated double sample circuits are provided for CCD output signal.
In CDS mode, the difference between the feed threw level of signal and the data level is sampled.
In clamp mode, the difference between the internal reference VCLP and the data level of signal is
sampled. Clamp pull the feed threw level into VCLP level when SHR is high.
„ Black Correction
Circuit to add an offset voltage to the sampled signal level. Voltage range of DAC which
generates Offset is ±321 mV(typ.) and its resolution is 8 bit.
„ MUX Block
MUX is a select switch that selects one signal from three ADC output signals sequentially.
The AK8443 has 2-channel mode and 3-channel mode. Each mode is selected by control
register.
„ ADC Block
The ADC coverts PGA output signal to digital data. The resolution is 16-bit and the maximum
conversion rate is 30MSPS. The output code is straight binary. The output data corresponding
to black is 0000h, and the data corresponding to white is FFFFh.
„ Output Control Block
The output control multiplexes a 16-bit word ADC data into two cycle 8-bit word data or four
cycle 4-bit word data.
„ Reference Voltage Gen1erator Block
All reference voltage is generated internally.
MS1280-E-00
2
2011/8