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AK8443 Datasheet, PDF (11/29 Pages) Asahi Kasei Microsystems – 16bit 30MSPS video ADC with CCD/CIS interface | |||
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[AK8443]
(AVDD=DVDD=3.0Vï½3.6V,Ta=0ï½70°C, 4 bit bus, unless otherwise specified)
No.
Item
1 MCLK cycle time (T)
2 MCLK Low width
3 MCLK High width
4 SHR,SHD cycle time
5 SHR pulse width
Pin Min. Typ. Max. Unit Condition
MCLK 33.3
2000 ï½ï½
MCLK 15
ï½ï½
MCLK 15
ï½ï½
SHR 199.8 6T 12000
3ch
ï½ï½
SHD 133.2 4T 8000
2ch
SHR
8
ï½ï½
SHR delay
6 ï¼referenced to SHDâï¼
SHR
2
ï½ï½
SHDâ delay
7 ï¼referenced to SHRâï¼
SHD
2
ï½ï½
8 SHD pulse width
SHD
8
ï½ï½
SHD setup time
9
SHD
0
ï½ï½
ï¼referenced to MCLKâï¼
SHD delay time
10
SHD
10
ï½ï½
ï¼referenced to MCLKâï¼
11 SHR aperture delay
SHR
2
ï½ï½
12 SHD aperture delay
SHD
2
ï½ï½
D0ï½7 delay time
hold
13 ï¼reference to MCLK âor D3ï½D0 2
12 ï½ï½ setup
MCLK âï¼
C=20pF
Pipeline delay
3ch mode
14
D3ï½D0
15
clock
(MCLK conversion)
2ch mode
SHD=âHâ
inhibition
period
15
ï¼ After referenced to
SHDâ, first MCLKâï¼
SHD 2T+10
ï½ï½ 3ch mode
2ch mode
MS1280-E-00
11
2011/8
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