AKD7782-A Datasheet, PDF (19/73 Pages) Asahi Kasei Microsystems – AK7782 Evaluation Board Rev.0

D[5:4]
D[3]
D[2]
D[1]
D[0]
CAD[1:0]
DAC-OUT1
DAC-OUT2
DAC-OUT3
DAC-OUT4
011 : SDOUT4
100 : SDOUT5
101 : SDOUT6
110 : SDOUT7
111 : SDOUTA
High/Low setup of AK7782’s CAD1,CAD0 pin
00 : Low, Low
01 : Low, High
10 : High, Low
11 : High, High
Output data source to DAC1
0 : SDOUT1
1 : SDOUT5
Output data source to DAC2
0 : SDOUT2
1 : SDOUT6
Output data source to DAC3
0 : SDOUT3
1 : SDOUT7
Output data source to DAC4
0 : SDOUT4
1 : SDOUTA
Table 10. FPGA Setting Table 4
AK4118A Setting Table:
Function
MCLK
CM
DIF
Description
Frequency of main clock output from AK4118A
00: 265fs
01: 256fs
10: 512fs
11: 128fs
Master clock operation mode of AK4118A
00: CM = 00
01: CM = 01
10: CM = 10
11: CM = 11
Audio I/O format of AK4118A
000: 16bit Right( O )
001: 18bit Right( O )
010: 20bit Right( O )
011: 24bit Right( O )
100: 24bit Left( O )
101: 24bit I2S( O )
110: 24bit Left( I )
111: 24bit I2S( I )
Table 11. AK4118A Setting Table
[AKD7782-A]
<KM106200>
- 19 -
2011/03