AKD7782-A Datasheet, PDF (18/73 Pages) Asahi Kasei Microsystems – AK7782 Evaluation Board Rev.0

[AKD7782-A]
D[1:0]
AK4118A-CLK
I/O clock setup of AK4118A
00 : Input
01 : AK7782-CLK
10 : SMUX1-CLK
11 : SMUX2-CLK
Table 8. FPGA Setting Table 2
ADDRESS：02
Bit
D[15]
Function
AK4118A-PDN
D[14]
DAC-PDN
D[13]
PADRSTN
D[12]
PSRCRSTN
D[11]
PDSPRSTN
D[10]
PCKRSTN
D[9]
PSRCSMUTE
D[8]
TESTI1
D[7]
TESTI2
D[6]
JX0
D[5:0]
Reserved
Description (Check Box only)
High/Low setup of AK4118A’s PDN pin
Default : H
High/Low setup of AK4359’s PDN pin
Default : H
High/Low setup of AK7782’s PADRSTN pin
Default : L
High/Low setup of AK7782’s PSRCRSTN pin
Default : L
High/Low setup of AK7782’s PDSPRSTN pin
Default : L
High/Low setup of AK7782’s PCKRSTN pin
Default : H
High/Low setup of AK7782’s PSRCSMUTE pin
Default : L
High/Low setup of AK7782’s TESTI1 pin
Default : L
High/Low setup of AK7782’s TESTI2 pin
Default : L
High/Low setup of AK7782’s JX0 pin
Default : L
Table 9. FPGA Setting Table 3
ADDRESS：03
Bit
D[15:14]
Function
SMUX1-CLK
D[13:12]
SMUX2-CLK
D[11:9]
SMUX1-DAT2
D[8:6]
SMUX2-DAT2
Description
I/O clock setup of SMUX1
00 : Input
01 : AK7782-CLK
10 : AK4118A-CLK
11 : SMUX2-CLK
I/O clock setup of SMUX2
00 : Input
01 : AK7782-CLK
10 : AK4118A-CLK
11 : SMUX1-CLK
Output data source to DAT2 pin of SMUX PORT1
000 : SDOUT1
001 : SDOUT2
010 : SDOUT3
011 : SDOUT4
100 : SDOUT5
101 : SDOUT6
110 : SDOUT7
111 : SDOUTA
Output data source to DAT2 pin of SMUX PORT2
000 : SDOUT1
001 : SDOUT2
010 : SDOUT3
<KM106200>
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2011/03