AK4385 Datasheet, PDF (19/21 Pages) Asahi Kasei Microsystems – 108dB 192kHz 24-Bit 2ch ΔΣ DAC

ASAHI KASEI
[AK4385]
1. Grounding and Power Supply Decoupling
VDD and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling
capacitor, especially 0.1µF ceramic capacitor for high frequency should be placed as near to VDD as possible. The
differential Voltage between VDD and VSS pins set the analog output range.
2. Analog Outputs
The analog outputs are full-differential outputs and 0.55 x VDD Vpp (typ) centered around the internal common voltage
(about AVDD/2). The differential outputs are summed externally, V_AOUT=(AOUT+)-(AOUT-) between AOUT+ and
AOUT-. If the summing gain is 1, the output range is 5.5Vpp (typ @VREFH=5V). The bias voltage of the external
summing circuit is supplied externally. The input data format is 2’s complement. The output voltage (V_AOUT) is a positive
full scale for 7FFFFF (@24bit) and a negative full scale for 800000H (@24bit). The ideal V_AOUT is 0V for 000000H
(@24bit).
The internal switched-capacitor filter and external low pass filter attenuate the noise generated by the delta-sigma
modulator beyond the audio passband. DC offset on AOUT+/- is eliminated without AC coupling since the analog
outputs are differential. Figure 10 and 11 show the example of external op-amp circuit summing the differential outputs.
AOUT-
AOUT+
Vop
BIAS
1k
0.1u
47u
1k
4.7k
3300p
4.7k
4.7k
R1
470p
Vop
R1
4.7k
470p
Analog
Out
When R1=200Ω
fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz
When R1=180Ω
fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
Figure 10. External 2^nd order LPF Circuit Example (using op-amp with single power supply)
AOUT-
AOUT+
4.7k
3300p
4.7k
4.7k
4.7k
R1
470p
+Vop
R1
470p ^-Vop
Analog
Out
When R1=200Ω
fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz
When R1=180Ω
fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
Figure 11. External 2^nd order LPF Circuit Example (using op-amp with dual power supplies)
MS0246-E-00
- 19 -
2003/07