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AK4385 Datasheet, PDF (15/21 Pages) Asahi Kasei Microsystems – 108dB 192kHz 24-Bit 2ch ΔΣ DAC | |||
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ASAHI KASEI
[AK4385]
 Reset Function
When RSTN=0, DAC is powered down but the internal register values are not initialized. The analog outputs go to
VCOM voltage and DZF pin goes to âHâ. Figure 7 shows the example of reset by RSTN bit.
RSTN bit
Internal
RSTN bit
Internal
State
D/A In
(Digital)
D/A Out
(Analog)
Clock In
MCLK,LRCK,BICK
DZF
Normal Operation
(1)
GD
3~4/fs (6)
2~3/fs (6)
Digital Block Power-down
Normal Operation
â0â data
(3) (2)
(3)
(4)
Donât care
2/fs(5)
GD (1)
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs go to VCOM voltage (VDD/2).
(3) Click noise occurs at the edges(ââ ââ) of the internal timing of RSTN bit. This noise is output even if â0â data is
input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = âLâ).
(5) DZF pins go to âHâ when the RSTN bit becomes â0â, and go to âLâ at 2/fs after RSTN bit becomes â1â.
(6) There is a delay, 3~4/fs from RSTN bit â0â to the internal RSTN bit â0â, and 2~3/fs from RSTN bit â1â to the
internal RSTN â1â.
Figure 7. Reset Sequence Example
MS0246-E-00
- 15 -
2003/07
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