AK4385 Datasheet, PDF (18/21 Pages) Asahi Kasei Microsystems – 108dB 192kHz 24-Bit 2ch ΔΣ DAC

ASAHI KASEI
[AK4385]
DZFM: Data Zero Detect Mode
0: Channel Separated Mode
1: Channel ANDed Mode
If the DZFM bit is set to “1”, the DZF pins of both channels go to “H” only when the input data at both
channels are continuously zeros for 8192 LRCK cycles.
Addr Register Name
D7
D6
D5
D4
D3
D2
D1
D0
02H Control 3
0
0
0
0
0
DZFB
0
0
default
0
0
0
0
0
0
0
0
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection
1: DZF goes “L” at Zero Detection
Addr
03H
04H
Register Name
Lch ATT
Rch ATT
default
D7
ATT7
ATT7
1
D6
ATT6
ATT6
1
D5
ATT5
ATT5
1
ATT = 20 log₁₀ (ATT_DATA / 255) [dB]
00H: Mute
D4
ATT4
ATT4
1
D3
ATT3
ATT3
1
D2
ATT2
ATT2
1
D1
ATT1
ATT1
1
D0
ATT0
ATT0
1
SYSTEM DESIGN
Figure 9 shows the system connection diagram. An evaluation board (AKD4385) is available in order to allow an easy
study on the layout of a surrounding circuit.
Master Clock
64fs
24bit Audio Data
fs
Reset & Power down
Micro-
controller
Digital Ground
1 MCLK
2 BICK
3 SDTI
4 LRCK
5 PDN
6 CSN
7 CCLK
8 CDTI
DZFL 16
DZFR 15
VDD 14
AK4385 ^{VSS 13}
AOUTL+ 12
AOUTL- 11
AOUTR+ 10
AOUTR- 9
0.1u ⁺ 10u
Lch
LPF
Rch
LPF
Analog Ground
Analog
Supply 5V
Lch
MUTE
Rch
MUTE
Lch Out
Rch Out
Figure 9. Typical Connection Diagram
Notes:
- LRCK = fs, BICK = 64fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and
capacitive load.
- All input pins except pull-down/pull-up pins should not be left floating.
MS0246-E-00
- 18 -
2003/07