AK5388_09 Datasheet, PDF (18/31 Pages) Asahi Kasei Microsystems – 120dB 24-bit 192kHz 4-Channel ADC

[AK5388]
CKS2 pin
L
L
L
L
H
H
H
H
CKS1 pin
L
L
H
H
L
L
H
H
CKS0 pin
L
H
L
H
L
H
L
H
M/S Pin
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
MCLK Frequency
Double Speed Mode
128fs (108KHz < fs ≤ 216KHz)
Quad Speed Mode
192fs (108KHz < fs ≤ 216KHz)
Normal Speed Mode
256fs (8KHz ≤ fs ≤ 54KHz)
Double Speed Mode
256fs (54KHz < fs ≤ 108KHz)
Auto (8KHz ≤ fs ≤ 216KHz)
Double Speed Mode
384fs (54KHz < fs ≤ 108KHz)
Normal Speed Mode
384fs (8KHz ≤ fs ≤ 54KHz)
Normal Speed Mode
512fs (8KHz < fs ≤ 54KHz)
Normal Speed Mode
768fs (8KHz ≤ fs ≤ 54KHz)
Table 4. MCLK Frequency
When changing MCLK frequency in master/slave mode, the AK5388 should reset by PDN pin = “L”. (ex.
12.288MHz(@fs=48kHz) at CKS1 pin = CKS0 pin = “L”.
■ Audio Interface Format
12 different audio data interface formats can be selected using the TDM1-0, M/S and DIF pins as shown in Table 5. The
audio data format can be selected by the DIF pin. In all formats the serial data is MSB-first, 2's compliment format. The
SDTO1/2 is clocked out on the falling edge of BICK.
In normal mode, Mode 0-1 are the slave mode, and BICK is available up to 128fs at fs=48kHz. BICK outputs 64fs clock
in Mode 2-3.
In TDM256 mode, all of the ADC’s serial data (four channels) is output from the SDTO1 pins. The SDTO2 output is
fixed to “L”. BICK should be fixed to 256fs. In slave mode, “H” time and “L” time of LRCK should be at least 1/256fs. In
master mode, “H” time (“L” time at I²S mode) of LRCK is 1/8fs (typ). TDM256 mode only supports 48kHz sampling.
In TDM128 mode, all of the ADC’s serial data (four channels) is output from the SDTO1 pin. The SDTO2 output is fixed
to “L”. BICK should be fixed to 128fs. In the slave mode, “H” time and “L” time of LRCK should be at least 1/128fs. In
master mode, “H” time (“L” time at I²S mode) of LRCK is 1/4fs (typ). TDM128 mode supports up to 192kHz sampling.
MS1096-E-01
- 18 -
2009/08