AK5388_09 Datasheet, PDF (12/31 Pages) Asahi Kasei Microsystems – 120dB 24-bit 192kHz 4-Channel ADC

[AK5388]
Parameter
Symbol
min
typ
max
Units
Audio Interface Timing (Master mode)
Normal mode (TDM1=“L”, TDM0=“L”)
BICK Frequency
fBCK
64fs
Hz
BICK Duty
dBCK
50
%
BICK “↓” to LRCK
tMBLR
−20
20
ns
BICK “↓” to SDTO1/2
tBSD
−20
20
ns
TDM256 mode (TDM1=“L”, TDM0=“H”)
BICK Frequency
fBCK
256fs
Hz
BICK Duty
(Note 16) dBCK
50
%
BICK “↓” to LRCK
tMBLR
−12
12
ns
BICK “↓” to SDTO1
(Note 15) tBSD
−20
20
ns
TDM128 mode (TDM1=“H”, TDM0=“H”)
(8KHz ≤ fs < 108KHz)
BICK Frequency
fBCK
128fs
Hz
BICK Duty
dBCK
50
%
BICK “↓” to LRCK
tMBLR
−12
12
ns
BICK “↓” to SDTO1
(Note 15) tBSD
−20
20
ns
TDM128 mode (TDM1=“H”, TDM0=“H”)
(108KHz < fs ≤ 216KHz)
BICK Frequency
fBCK
128fs
Hz
BICK Duty
dBCK
50
%
BICK “↓” to LRCK
tMBLR
−6
6
ns
BICK “↓” to SDTO1
tBSD
−10
10
ns
Power-Down & Reset Timing
PDN Pulse Width
(Note 17) tPD
150
ns
PDN “↑” to SDTO1/2 valid
(Note 18) tPDV
516
1/fs
Note 14. BICK rising edge must not occur at the same time as LRCK edge.
Note 15. SDTO2 output is fixed to “L”.
Note 16. This value is MCLK=512fs. Duty cycle is not guaranteed when MCLK=256fs/384fs.
Note 17. The AK5388 can be reset by bringing the PDN pin = “L”.
Note 18. This cycle is the number of LRCK rising edges from the PDN pin = “H”. The value is when the AK5388 is in
master mode. In case of in slave mode, the value will be 1LRCK clock cycle (1/fs) longer.
MS1096-E-01
- 12 -
2009/08