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AK4116 Datasheet, PDF (17/36 Pages) Asahi Kasei Microsystems – LOW POWER 48KHZ DIGITAL AUDIO RECEIVER | |||
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ASAHI KASEI
[AK4116]
 Interrupt Handling
There are eight events which cause the INT1-0 pins to go âHâ.
1. UNLCK: PLL unlock state detect
â1â when the PLL loses lock. The AK4116 loses lock when the distance between two preambles is
not correct or when those preambles are not correct.
2. PAR: Parity error or biphase coding error detection
â1â when parity error or biphase coding error is detected, updated every sub-frame cycle. Reading
this register resets it.
3. AUTO: Non-PCM or DTS-CD Bit Stream detection
The OR function of NPCM and DTSCD bits is output to the AUTO bit.
4. V:
Validity flag detection
â1â when validity flag is detected. Updated every sub-frame cycle.
5. AUDION: Non-audio detection
â1â when the âAUDIOâ bit in recovered channel status indicates â1â. Updated every block cycle.
6. STC: Sampling frequency or pre-emphasis information change detection
â1â when FS3-0 or PEM bit changes. Reading this register resets it.
7. QINT: U bit (Q-subcode) sync flag
â1â when the Q-subcode differs from old one, and stays â1â until this register is read. Updated
every sync code cycle for Q-subcode. Reading this register resets it.
8. CINT: Channel status sync flag
â1â when received C bits differ from old ones, and stays â1â until this register is read. Updated
every block cycle. Reading this register resets it.
INT1-0 pins output an ORâed signal based on the above eight interrupt events. When masked, the interrupt event does not
affect the operation of the INT1-0 pins (the masks do not affect the resisters (UNLCK, PAR, etc.) themselves). Once
INT0 pin goes to âHâ, it maintains âHâ for 1024 cycles (this value can be changed by the EFH1-0 bits) after all events
not masked by mask bits are cleared. INT1 pin immediately goes to âLâ when those events are cleared.
UNLCK, AUTO, V and AUDION bits indicate the interrupt status events above in real time. Once PAR, STC, QINT or
CINT bit goes to â1â, it stays â1â until the register is read. INT pin holds âHâ for one sub-frame, then goes to âLâ in this
case.
When the AK4116 loses lock, the channel status bits are initialized. In this initial state, INT0 outputs the ORâed signal
between UNLCK and PAR bits. INT1 outputs the ORâed signal to AUTO, V and AUDION. INT1-0 pins are âLâ when
the PLL is OFF (Clock Operation Mode 1).
UNLCK
1
0
0
Event
PAR
x
1
0
Others
x
x
x
SDTO Pin
âLâ
Previous Data
Output
Table 6. Interrupt handling
MS0156-E-02
- 17 -
2004/04
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