AK4116 Datasheet, PDF (10/36 Pages) Asahi Kasei Microsystems – LOW POWER 48KHZ DIGITAL AUDIO RECEIVER

ASAHI KASEI
[AK4116]
OPERATION OVERVIEW
„ Non-PCM (AC-3, MPEG, etc.) and DTS-CD Bitstream Detection
The AK4116 has a Non-PCM steam auto-detection function. When the 32-bit mode Non-PCM preamble based on Dolby
“AC-3 Data Stream in IEC60958 Interface” is detected, the NPCM bit goes to “1”. The 96-bit sync code consists of
0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the NPCM to “1”. Once the
NPCM is set to “1”, it will remain “1” until 4096 frames pass through the chip without an additional sync pattern being
detected (Timing diagram: Figure 26 and Figure 27). When those preambles are detected, the burst preambles Pc (burst
information: Table 8) and Pd (length code: Table 9) that follow those sync codes are stored to registers. The AK4116 also
has a DTS-CD bitstream auto-detection function. When AK4116 detects DTS-CD bitstreams, the DTSCD bit goes to “1”.
If the next sync code does not occur within 4096 frames, the DTSCD bit goes to “0” until either the AK4116 detects the
stream again. OR’ed value of the NPCM and DTSCD bits are output to the AUTO bit. The AK4116 detects 14bit sync
word of a DTS-CD bitstearm, while it does not detect 16bit sync word (0x7FFE8001).
„ Clock Recovery
The on-chip, low jitter PLL has a wide lock range of 32kHz to 48kHz and a lock time of less than 20ms. The AK4116 has
a sampling frequency detect function (32kHz, 44.1kHz and 48kHz) that uses either clock comparison against the X’tal
oscillator or the channel status information. The PLL loses lock when the received sync interval is incorrect.
„ Clock Operation Mode
The AK4116 has two sources for MCKO and SDTO.
1) MCKO and SDTO source is recovered by PLL from RX input.
2) MCKO source is X’tal or External clock. SDTO source is DAUX input.
The CM1-0 bits select the clock operation mode (Table 1). In Mode 2, the clock source is switched from PLL to X'tal
when the PLL loses lock. In Mode3, even though the clock source is fixed to X'tal, the PLL is also operating. This allows
the monitoring of recovered data such as C bits. For Mode2 and 3, it is recommended that the X’tal frequency and PLL
recovery frequency be set differently.
Mode
0
1
2
3
CM1
0
0
1
1
CM0
0
1
0
1
UNLCK
-
-
0
1
-
PLL
X'tal Clock source SDTO
ON ON(Note)
PLL
RX
Default
OFF
ON
X'tal
DAUX
ON
ON
PLL
RX
ON
ON
X'tal
DAUX
ON
ON
X'tal
DAUX
ON: Oscillation (Power-up), OFF: STOP (Power-down)
Note : When the X’tal is not used as clock comparison for fs detection (i.e. XTL1,0= “1,1”), the X’tal is off.
Table 1. Clock Operation Mode select
MS0156-E-02
- 10 -
2004/04