AK5388 Datasheet, PDF (16/27 Pages) Asahi Kasei Microsystems – 120dB 24-bit 192kHz 4-Channel ADC

[AK5388]
OPERATION OVERVIEW
■ System Clock
MCLK (256fs/384fs/512fs), BICK (48fs∼) and LRCK (fs) clocks are required in slave mode. The LRCK clock input must
be synchronized with MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling
frequency and the system clock frequency. MCLK frequency is selected by CKS1-0 pins as shown in Table 2.
Since the AK5388 includes a phase detection circuit for LRCK, the AK5388 is reset automatically when the
synchronization is out of phase after changing the clock frequencies.
All external clocks (MCLK, BICK and LRCK) must be present unless the PDN pin = “L”. If these clocks are not
provided, the AK5388 may draw excess current due to its use of internal dynamically refreshed logic. If the external
clocks are not present, place the AK5388 in power-down mode (PDN pin = “L”). In master mode, the master clock
(MCLK) must be provided unless PDN pin = “L”.
fs
32kHz
48kHz
96kHz
192kHz
128fs
N/A
N/A
N/A
24.576MHz
192fs
N/A
N/A
N/A
36.864MHz
MCLK
256fs
384fs
8.192MHz 12.288MHz
12.288MHz 18.432MHz
24.576MHz
N/A
N/A
N/A
Table 1. System Clock Example (Slave Mode)
512fs
768fs
16.384MHz 24.576MHz
24.576MHz 36.864MHz
N/A
N/A
N/A
N/A
(N/A: Not available)
fs
32kHz
48kHz
96kHz
192kHz
128fs
N/A
N/A
N/A
24.576MHz
192fs
N/A
N/A
N/A
36.864MHz
MCLK
256fs
384fs
8.192MHz 12.288MHz
12.288MHz 18.432MHz
24.576MHz 36.864MHz
N/A
N/A
Table 2. System Clock Example (Master Mode)
512fs
768fs
16.384MHz 24.576MHz
24.576MHz 36.864MHz
N/A
N/A
N/A
N/A
(N/A: Not available)
fs
32kHz
48kHz
96kHz
192kHz
128fs
N/A
N/A
N/A
24.576MHz
192fs
N/A
N/A
N/A
36.864MHz
MCLK
256fs
384fs
N/A
N/A
N/A
N/A
24.576MHz 36.864MHz
N/A
N/A
Table 3. System Clock Example (Auto Mode)
512fs
768fs
16.384MHz 24.576MHz
24.576MHz 36.864MHz
N/A
N/A
N/A
N/A
(N/A: Not available)
Rev. 0.3
- 16 -
2007/10