AK5388 Datasheet, PDF (11/27 Pages) Asahi Kasei Microsystems – 120dB 24-bit 192kHz 4-Channel ADC

Parameter
Audio Interface Timing (Slave mode)
Normal mode (TDM1=“L”, TDM0=“L”)
BICK Period
Normal Speed Mode
Double , Quad Speed Mode
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
(Note 14)
BICK “↑” to LRCK Edge
(Note 14)
LRCK to SDTO1/2 (MSB) (Except I²S mode)
BICK “↓” to SDTO1/2
TDM256 mode (TDM1=“L”, TDM0=“H”)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
BICK “↓” to SDTO1/2
(Note 14)
(Note 14)
TDM128 mode (TDM1=“H”, TDM0=“H”)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
BICK “↓” to SDTO1
(Note 14)
(Note 14)
(Note 15)
Audio Interface Timing (Master mode)
Normal mode (TDM1=“L”, TDM0=“L”)
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO1/2
TDM256 mode (TDM1=“L”, TDM0=“H”)
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO1/2
(Note 16)
TDM128 mode (TDM1=“H”, TDM0=“H”)
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO1
(Note 15)
Power-Down & Reset Timing
PDN Pulse Width
PDN “↑” to SDTO1/2 valid
(Note 17)
(Note 18)
Symbol
TBCK
TBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
fBCK
dBCK
tMBLR
tBSD
fBCK
dBCK
tMBLR
tBSD
fBCK
dBCK
tMBLR
tBSD
tPD
tPDV
min
1/128fs
1/64fs
32
32
20
20
1/256fs
16
16
16
16
1/128fs
TBD
TBD
TBD
TBD
−20
−20
−12
−20
−TBD
−TBD
150
typ
64fs
50
256fs
50
128fs
50
516
[AK5388]
max
Units
ns
ns
ns
ns
ns
ns
20
ns
20
ns
ns
ns
ns
ns
ns
10
ns
ns
ns
ns
ns
ns
TBD
ns
Hz
%
20
ns
20
ns
Hz
%
12
ns
20
ns
Hz
%
TBD
ns
TBD
ns
ns
1/fs
Rev. 0.3
- 11 -
2007/10