AK5388 Datasheet, PDF (12/27 Pages) Asahi Kasei Microsystems – 120dB 24-bit 192kHz 4-Channel ADC

Note 14. BICK rising edge must not occur at the same time as LRCK edge.
Note 15. SDTO2 output is fixed to “L”.
Note 16. This value is MCLK=512fs. Duty cycle is not guaranteed when MCLK=256fs/384fs.
Note 17. The AK5388 can be reset by bringing the PDN pin = “L”.
Note 18. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
[AK5388]
■ Timing Diagram
MCLK
LRCK
BICK
MCLK
LRCK
BICK
1/fCLK
tCLKH
tCLKL
1/fs
tBCK
tBCKH
tBCKL
Figure 1. Clock Timing (TDM0 pin = “L”)
1/fCLK
tCLKH
tCLKL
1/fs
tLRH
tLRL
tBCK
tBCKH
tBCKL
Figure 2. Clock Timing (TDM0 pin = “H”)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
Rev. 0.3
- 12 -
2007/10