AK4348 Datasheet, PDF (16/31 Pages) Asahi Kasei Microsystems – 3.3V 192kHz 24-Bit 8-Channel DAC

ASAHI KASEI
[AK4348]
„ De-emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs). The digital de-emphasis
filter is always off when the AK4348 is operated in double or quad speed modes. In serial control mode, the DEM0-1 bits
are valid for the DAC enabled by the DEMA-D bits. In parallel control mode, the DEM0-1 pins are valid.
DEM1
0
0
1
1
DEM0
0
1
0
1
Mode
44.1kHz
OFF
48kHz
32kHz
Table 9. De-emphasis Filter Control (Normal Speed Mode)
„ Output Volume
The AK4348 includes channel independent digital volume controls (ATT) with 256 linear steps, including MUTE. The
volume controls are in front of the DAC and can attenuate the input data from 0dB to –48dB, and mute. When changing
levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. The transition time
of 1 level and all 256 levels is shown in Table 10. The attenuation level is calculated by ATT = 20 log₁₀ (ATT_DATA /
255) [dB] and MUTE at ATT_DATA = “0”.
Sampling Speed
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Transition Time
1 Level
255 to 0
4LRCK
1020LRCK
8LRCK
2040LRCK
16LRCK
4080LRCK
„ Zero Detection
Table 10. ATT Transition time
When the input data at all channels are continuously zeros for 8192 LRCK cycles, the AK4348 has a Zero Detect function
detailed in Table 11. The DZF pin immediately goes to “L” if the input data for each channel is not zero after the DZF pin
is “H”. If the RSTN bit is “0”, the DZF pin goes to “H”. The DZF pin goes to “L” after 4 to 5LRCK cycles if the input data
of each channel is not zero after the RSTN bit returns to “1”. The Zero Detect function can be disabled by the DZFE bit.
In this case, both DZF pins are always “L”. When one of the PW1-4 bits is set to “0”, the input data of the DAC for which
the PW bit is set to “0” should be zero in order to enable zero detection of the other channels. When all PW1-4 bits are set
to “0”, both DZF pins are fixed to “L”. The DZFB bit can invert the polarity of the DZF pin. In parallel control mode, the
zero detect function is disabled and the DZF1 pin is fixed to “L”.
DZF Pin
DZF1
DZF2
Operations
AND’ed output of zero detection flag of each channel set to “1” in 0CH register
AND’ed output of zero detection flag of each channel set to “1” in 0DH register
Table 11. DZF pins Operation
MS0532-E-00
- 16 -
2006/07